[PATCH] D143335: [AMDGPU] Use instruction order in machine function to process workList of moveToVALU

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:6166
+      return false;
+    const MachineBasicBlock *BA = InstA->getParent();
+    const MachineBasicBlock *BB = InstB->getParent();
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Do you really need to guarantee the order between different basic blocks? If so, surely you need some kind of topological ordering, not just based on BB number. (And what if there are cycles in the CFG?)


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:6185
+    // in the machine function.
+    llvm::stable_sort(Worklist, miCompare);
+    auto iter = Worklist.begin();
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Sorting the whole worklist every time round this loop is not acceptable. You need to find a more efficient way of doing this.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143335/new/

https://reviews.llvm.org/D143335