[PATCH] D143362: [RISCV] Make 'c.addi x0, imm' an alias for 'c.nop imm'.

[Craig Topper via Phabricator via llvm-commits]

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Instead of making it an AsmParserOnly instruction, make it an alias.
This makes printing consistent with disassembly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143362

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/MC/RISCV/rvc-hints-valid.s


Index: llvm/test/MC/RISCV/rvc-hints-valid.s
===================================================================
--- llvm/test/MC/RISCV/rvc-hints-valid.s
+++ llvm/test/MC/RISCV/rvc-hints-valid.s
@@ -4,21 +4,20 @@
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
 # RUN:     | llvm-objdump -M no-aliases -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
 # RUN:     | llvm-objdump -M no-aliases -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
 # RUN:     | llvm-objdump -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: c.nop 8
 # CHECK-ASM: encoding: [0x21,0x00]
 c.nop 8
 
-# CHECK-ASM: c.addi zero, 7
+# CHECK-ASM-AND-OBJ: c.nop 7
 # CHECK-ASM: encoding: [0x1d,0x00]
-# CHECK-OBJ: c.nop 7
 c.addi x0, 7
 
 # CHECK-ASM-AND-OBJ: c.addi a0, 0
Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -614,16 +614,6 @@
   let DecoderMethod = "decodeRVCInstrSImm";
 }
 
-// Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
-def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
-                                (ins GPRX0:$rd, simm6nonzero:$imm),
-                                "c.addi", "$rd, $imm">,
-                     Sched<[WriteIALU, ReadIALU]> {
-  let Constraints = "$rd = $rd_wb";
-  let Inst{6-2} = imm{4-0};
-  let isAsmParserOnly = 1;
-}
-
 def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
                                       (ins GPRNoX0:$rd, immzero:$imm),
                                       "c.addi", "$rd, $imm">,
@@ -712,6 +702,11 @@
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
+let Predicates = [HasStdExtCOrZca, HasRVCHints] in {
+// Just a different syntax for the c.nop hint: c.addi x0, simm6 vs c.nop simm6.
+def : InstAlias<"c.addi x0, $imm", (C_NOP_HINT simm6nonzero:$imm), 0>;
+}
+
 let Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl] in {
 def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
 def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;


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