[PATCH] D142656: [SVE][codegen] Add pattern for SVE multiply-add accumulate

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Hi All, I could have saved you some time here but am only just catching up on code reviews.  Firstly, whilst the MachineCombine argument is not totally irrelevant I'm going to dismiss it for now because as @sushgokh pointed out, this is not how we currently do such things for SVE.  For the most part doing this during ISEL gets us mostly what we need.

At least part of the motivation for this patch looks to be to allow a better choice as to when to use MLA or MAD. We handle this by not making the choice during ISEL but instead selecting a pseudo instruction that gets expanded after register allocation when we have access to more information. You'll see an example of this for the floating point side of things whereby FMLA_ZPZZ_UNDEF_D is emitted that is later expanded into one of FMLA_ZPmZZ_D, FMAD_ZPmZZ_D or a MOVPRFX'd FMLA_ZPmZZ_D depending on which registers, if any, the register allocation has chosen to reuse for the result.

@sushgokh: I don't know how familiar you are with this logic so if you prefer me to upload a base implementation for you to build on then please just shout.


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  https://reviews.llvm.org/D142656/new/

https://reviews.llvm.org/D142656