[PATCH] D143335: [AMDGPU] Use instruction order in machine function to process workList of moveToVALU

[krishna chaitanya sankisa via Phabricator via llvm-commits]

skc7 created this revision.
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Update moveToVALU method to accept vector of instructions as worklist. 
Sort the Worklist in ascending order of instructions as per machine function before picking one instruction to process.

Instruction will be moved to VALU or legalizeOperands is called on it before all the instruction prior to it in machine function are processed. legalizeOperands will be able to process the operands together with this change.

This patch is required to legalize rsrc and soffset of MBUF instruction together and create single waterfall loop. Prerequisite for D141030 <https://reviews.llvm.org/D141030>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143335

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/add3.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
  llvm/test/CodeGen/AMDGPU/shl.ll
  llvm/test/CodeGen/AMDGPU/sra.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/srl.ll
  llvm/test/CodeGen/AMDGPU/sub.ll
  llvm/test/CodeGen/AMDGPU/udiv.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/udivrem.ll
  llvm/test/CodeGen/AMDGPU/urem.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll