[llvm] d4a8a59 - [AArch64][GlobalISel] Selection for i8 buildvectors
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 4 08:11:34 PST 2023
Author: David Green
Date: 2023-02-04T16:11:29Z
New Revision: d4a8a59441052165ccdd6ca493ce124be5e80d9e
URL: https://github.com/llvm/llvm-project/commit/d4a8a59441052165ccdd6ca493ce124be5e80d9e
DIFF: https://github.com/llvm/llvm-project/commit/d4a8a59441052165ccdd6ca493ce124be5e80d9e.diff
LOG: [AArch64][GlobalISel] Selection for i8 buildvectors
Legalization for i8 buildvectors is available (as in
615695de27e417d6b444cd983e6f636373afc8c9), but selection
would fail due to i8 types not being handled. This adds
basic support like other type sizes.
Differential Revision: https://reviews.llvm.org/D143002
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 58e89010c1390..1f9a50b2b02c0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3994,6 +3994,8 @@ MachineInstr *AArch64InstructionSelector::emitScalarToVector(
};
switch (EltSize) {
+ case 8:
+ return BuildFn(AArch64::bsub);
case 16:
return BuildFn(AArch64::hsub);
case 32:
@@ -5543,7 +5545,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
if (tryOptBuildVecToSubregToReg(I, MRI))
return true;
- if (EltSize < 16 || EltSize > 64)
+ if (EltSize != 8 && EltSize != 16 && EltSize != 32 && EltSize != 64)
return false; // Don't support all element types yet.
const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
index 4347cfe79ffed..0c0f9ae896c7d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
@@ -308,6 +308,91 @@ body: |
RET_ReallyLR implicit $d0
...
---
+name: test_v16s8_unmerge
+alignment: 4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0
+ ; CHECK-LABEL: name: test_v16s8_unmerge
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
+ ; CHECK-NEXT: [[DUPi8_:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 1
+ ; CHECK-NEXT: [[DUPi8_1:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 2
+ ; CHECK-NEXT: [[DUPi8_2:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 3
+ ; CHECK-NEXT: [[DUPi8_3:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 4
+ ; CHECK-NEXT: [[DUPi8_4:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 5
+ ; CHECK-NEXT: [[DUPi8_5:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 6
+ ; CHECK-NEXT: [[DUPi8_6:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 7
+ ; CHECK-NEXT: [[DUPi8_7:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 8
+ ; CHECK-NEXT: [[DUPi8_8:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 9
+ ; CHECK-NEXT: [[DUPi8_9:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 10
+ ; CHECK-NEXT: [[DUPi8_10:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 11
+ ; CHECK-NEXT: [[DUPi8_11:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 12
+ ; CHECK-NEXT: [[DUPi8_12:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 13
+ ; CHECK-NEXT: [[DUPi8_13:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 14
+ ; CHECK-NEXT: [[DUPi8_14:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 15
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.bsub
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi8_]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane:%[0-9]+]]:fpr128 = INSvi8lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi8_1]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane1:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane]], 2, [[INSERT_SUBREG2]], 0
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[DUPi8_2]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane2:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane1]], 3, [[INSERT_SUBREG3]], 0
+ ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[DUPi8_3]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane3:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane2]], 4, [[INSERT_SUBREG4]], 0
+ ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[DUPi8_4]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane4:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane3]], 5, [[INSERT_SUBREG5]], 0
+ ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[DUPi8_5]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane5:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane4]], 6, [[INSERT_SUBREG6]], 0
+ ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[DUPi8_6]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane6:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane5]], 7, [[INSERT_SUBREG7]], 0
+ ; CHECK-NEXT: [[DEF8:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG8:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF8]], [[DUPi8_7]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane7:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane6]], 8, [[INSERT_SUBREG8]], 0
+ ; CHECK-NEXT: [[DEF9:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG9:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF9]], [[DUPi8_8]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane8:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane7]], 9, [[INSERT_SUBREG9]], 0
+ ; CHECK-NEXT: [[DEF10:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG10:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF10]], [[DUPi8_9]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane9:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane8]], 10, [[INSERT_SUBREG10]], 0
+ ; CHECK-NEXT: [[DEF11:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG11:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF11]], [[DUPi8_10]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane10:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane9]], 11, [[INSERT_SUBREG11]], 0
+ ; CHECK-NEXT: [[DEF12:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG12:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF12]], [[DUPi8_11]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane11:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane10]], 12, [[INSERT_SUBREG12]], 0
+ ; CHECK-NEXT: [[DEF13:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG13:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF13]], [[DUPi8_12]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane12:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane11]], 13, [[INSERT_SUBREG13]], 0
+ ; CHECK-NEXT: [[DEF14:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG14:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF14]], [[DUPi8_13]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane13:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane12]], 14, [[INSERT_SUBREG14]], 0
+ ; CHECK-NEXT: [[DEF15:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG15:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF15]], [[DUPi8_14]], %subreg.bsub
+ ; CHECK-NEXT: [[INSvi8lane14:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane13]], 15, [[INSERT_SUBREG15]], 0
+ ; CHECK-NEXT: $q0 = COPY [[INSvi8lane14]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:fpr(<16 x s8>) = COPY $q0
+ %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8) = G_UNMERGE_VALUES %0(<16 x s8>)
+
+ %1:fpr(<16 x s8>) = G_BUILD_VECTOR %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8)
+ $q0 = COPY %1(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
+---
name: test_vecsplit_2v2s32_v4s32
alignment: 4
legalized: true
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