[llvm] 0b82746 - [AMDGPU] GFX11: rename VALU pknorm instructions to pk_norm
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 3 08:32:38 PST 2023
Author: Jay Foad
Date: 2023-02-03T16:32:29Z
New Revision: 0b82746567e9c75a750e146bc27bd90c53e85829
URL: https://github.com/llvm/llvm-project/commit/0b82746567e9c75a750e146bc27bd90c53e85829
DIFF: https://github.com/llvm/llvm-project/commit/0b82746567e9c75a750e146bc27bd90c53e85829.diff
LOG: [AMDGPU] GFX11: rename VALU pknorm instructions to pk_norm
GFX11 renames:
v_cvt_pknorm_i16_f32 to v_cvt_pk_norm_i16_f32
v_cvt_pknorm_u16_f32 to v_cvt_pk_norm_u16_f32
Accept the old name as an alias.
Fixes https://github.com/llvm/llvm-project/issues/60334
Differential Revision: https://reviews.llvm.org/D143266
Added:
llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
Modified:
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index b30340b155f64..10a7f0661f23b 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1477,19 +1477,19 @@ defm V_FMAMK_F16_t16 : VOP2Only_Real_MADK_gfx11_with_name<0x037, "v_fmamk_
defm V_FMAAK_F16_t16 : VOP2Only_Real_MADK_gfx11_with_name<0x038, "v_fmaak_f16">;
// VOP3 only.
-defm V_CNDMASK_B16 : VOP3Only_Realtriple_gfx11<0x25d>;
-defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11<0x31c>;
-defm V_BFM_B32 : VOP3Only_Realtriple_gfx11<0x31d>;
-defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11<0x31e>;
-defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11<0x31f>;
-defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11<0x320>;
-defm V_CVT_PKNORM_I16_F32 : VOP3Only_Realtriple_gfx11<0x321>;
-defm V_CVT_PKNORM_U16_F32 : VOP3Only_Realtriple_gfx11<0x322>;
-defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11<0x323>;
-defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11<0x324>;
-defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x300>;
-defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x301>;
-defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x302>;
+defm V_CNDMASK_B16 : VOP3Only_Realtriple_gfx11<0x25d>;
+defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11<0x31c>;
+defm V_BFM_B32 : VOP3Only_Realtriple_gfx11<0x31d>;
+defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11<0x31e>;
+defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11<0x31f>;
+defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11<0x320>;
+defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
+defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
+defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11<0x323>;
+defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11<0x324>;
+defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x300>;
+defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x301>;
+defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11<0x302>;
let SubtargetPredicate = isGFX11Plus in {
defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
index d236874de5669..a0beee1c7eb66 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
@@ -1450,184 +1450,184 @@ v_cvt_pk_u8_f32 v5, src_scc, vcc_lo, -1
v_cvt_pk_u8_f32 v255, -|0xaf123456|, vcc_hi, null
// GFX11: encoding: [0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf]
-v_cvt_pknorm_i16_f16 v5, v1, v2
+v_cvt_pk_norm_i16_f16 v5, v1, v2
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
-v_cvt_pknorm_i16_f16 v5, v255, v255
+v_cvt_pk_norm_i16_f16 v5, v255, v255
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0xff,0xff,0x03,0x00]
-v_cvt_pknorm_i16_f16 v5, s1, s2
+v_cvt_pk_norm_i16_f16 v5, s1, s2
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, s105, s105
+v_cvt_pk_norm_i16_f16 v5, s105, s105
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x69,0xd2,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, vcc_lo, ttmp15
+v_cvt_pk_norm_i16_f16 v5, vcc_lo, ttmp15
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x6a,0xf6,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, vcc_hi, 0xfe0b
+v_cvt_pk_norm_i16_f16 v5, vcc_hi, 0xfe0b
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, ttmp15, src_scc
+v_cvt_pk_norm_i16_f16 v5, ttmp15, src_scc
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x7b,0xfa,0x01,0x00]
-v_cvt_pknorm_i16_f16 v5, m0, 0.5
+v_cvt_pk_norm_i16_f16 v5, m0, 0.5
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x7d,0xe0,0x01,0x00]
-v_cvt_pknorm_i16_f16 v5, exec_lo, -1
+v_cvt_pk_norm_i16_f16 v5, exec_lo, -1
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x7e,0x82,0x01,0x00]
-v_cvt_pknorm_i16_f16 v5, |exec_hi|, null
+v_cvt_pk_norm_i16_f16 v5, |exec_hi|, null
// GFX11: encoding: [0x05,0x01,0x12,0xd7,0x7f,0xf8,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, null, exec_lo
+v_cvt_pk_norm_i16_f16 v5, null, exec_lo
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0x7c,0xfc,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, -1, exec_hi
+v_cvt_pk_norm_i16_f16 v5, -1, exec_hi
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0xc1,0xfe,0x00,0x00]
-v_cvt_pknorm_i16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+v_cvt_pk_norm_i16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
// GFX11: encoding: [0x05,0x00,0x12,0xd7,0xf0,0xfa,0x00,0x40]
-v_cvt_pknorm_i16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+v_cvt_pk_norm_i16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
// GFX11: encoding: [0x05,0x0a,0x12,0xd7,0xfd,0xd4,0x00,0x20]
-v_cvt_pknorm_i16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+v_cvt_pk_norm_i16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
// GFX11: encoding: [0xff,0x13,0x12,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, v1, v2
+v_cvt_pk_norm_i16_f32 v5, v1, v2
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00]
-v_cvt_pknorm_i16_f32 v5, v255, v255
+v_cvt_pk_norm_i16_f32 v5, v255, v255
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00]
-v_cvt_pknorm_i16_f32 v5, s1, s2
+v_cvt_pk_norm_i16_f32 v5, s1, s2
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, s105, s105
+v_cvt_pk_norm_i16_f32 v5, s105, s105
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, vcc_lo, ttmp15
+v_cvt_pk_norm_i16_f32 v5, vcc_lo, ttmp15
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, vcc_hi, 0xaf123456
+v_cvt_pk_norm_i16_f32 v5, vcc_hi, 0xaf123456
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
-v_cvt_pknorm_i16_f32 v5, ttmp15, src_scc
+v_cvt_pk_norm_i16_f32 v5, ttmp15, src_scc
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00]
-v_cvt_pknorm_i16_f32 v5, m0, 0.5
+v_cvt_pk_norm_i16_f32 v5, m0, 0.5
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00]
-v_cvt_pknorm_i16_f32 v5, exec_lo, -1
+v_cvt_pk_norm_i16_f32 v5, exec_lo, -1
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00]
-v_cvt_pknorm_i16_f32 v5, |exec_hi|, null
+v_cvt_pk_norm_i16_f32 v5, |exec_hi|, null
// GFX11: encoding: [0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, null, exec_lo
+v_cvt_pk_norm_i16_f32 v5, null, exec_lo
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, -1, exec_hi
+v_cvt_pk_norm_i16_f32 v5, -1, exec_hi
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00]
-v_cvt_pknorm_i16_f32 v5, 0.5, -m0
+v_cvt_pk_norm_i16_f32 v5, 0.5, -m0
// GFX11: encoding: [0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40]
-v_cvt_pknorm_i16_f32 v5, -src_scc, |vcc_lo|
+v_cvt_pk_norm_i16_f32 v5, -src_scc, |vcc_lo|
// GFX11: encoding: [0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20]
-v_cvt_pknorm_i16_f32 v255, -|0xaf123456|, -|vcc_hi|
+v_cvt_pk_norm_i16_f32 v255, -|0xaf123456|, -|vcc_hi|
// GFX11: encoding: [0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
-v_cvt_pknorm_u16_f16 v5, v1, v2
+v_cvt_pk_norm_u16_f16 v5, v1, v2
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
-v_cvt_pknorm_u16_f16 v5, v255, v255
+v_cvt_pk_norm_u16_f16 v5, v255, v255
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0xff,0xff,0x03,0x00]
-v_cvt_pknorm_u16_f16 v5, s1, s2
+v_cvt_pk_norm_u16_f16 v5, s1, s2
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, s105, s105
+v_cvt_pk_norm_u16_f16 v5, s105, s105
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x69,0xd2,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, vcc_lo, ttmp15
+v_cvt_pk_norm_u16_f16 v5, vcc_lo, ttmp15
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x6a,0xf6,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, vcc_hi, 0xfe0b
+v_cvt_pk_norm_u16_f16 v5, vcc_hi, 0xfe0b
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, ttmp15, src_scc
+v_cvt_pk_norm_u16_f16 v5, ttmp15, src_scc
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x7b,0xfa,0x01,0x00]
-v_cvt_pknorm_u16_f16 v5, m0, 0.5
+v_cvt_pk_norm_u16_f16 v5, m0, 0.5
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x7d,0xe0,0x01,0x00]
-v_cvt_pknorm_u16_f16 v5, exec_lo, -1
+v_cvt_pk_norm_u16_f16 v5, exec_lo, -1
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x7e,0x82,0x01,0x00]
-v_cvt_pknorm_u16_f16 v5, |exec_hi|, null
+v_cvt_pk_norm_u16_f16 v5, |exec_hi|, null
// GFX11: encoding: [0x05,0x01,0x13,0xd7,0x7f,0xf8,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, null, exec_lo
+v_cvt_pk_norm_u16_f16 v5, null, exec_lo
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0x7c,0xfc,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, -1, exec_hi
+v_cvt_pk_norm_u16_f16 v5, -1, exec_hi
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0xc1,0xfe,0x00,0x00]
-v_cvt_pknorm_u16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
+v_cvt_pk_norm_u16_f16 v5, 0.5, -m0 op_sel:[0,0,0]
// GFX11: encoding: [0x05,0x00,0x13,0xd7,0xf0,0xfa,0x00,0x40]
-v_cvt_pknorm_u16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
+v_cvt_pk_norm_u16_f16 v5, -src_scc, |vcc_lo| op_sel:[1,0,0]
// GFX11: encoding: [0x05,0x0a,0x13,0xd7,0xfd,0xd4,0x00,0x20]
-v_cvt_pknorm_u16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
+v_cvt_pk_norm_u16_f16 v255, -|0xfe0b|, -|vcc_hi| op_sel:[0,1,0]
// GFX11: encoding: [0xff,0x13,0x13,0xd7,0xff,0xd6,0x00,0x60,0x0b,0xfe,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, v1, v2
+v_cvt_pk_norm_u16_f32 v5, v1, v2
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00]
-v_cvt_pknorm_u16_f32 v5, v255, v255
+v_cvt_pk_norm_u16_f32 v5, v255, v255
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00]
-v_cvt_pknorm_u16_f32 v5, s1, s2
+v_cvt_pk_norm_u16_f32 v5, s1, s2
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, s105, s105
+v_cvt_pk_norm_u16_f32 v5, s105, s105
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, vcc_lo, ttmp15
+v_cvt_pk_norm_u16_f32 v5, vcc_lo, ttmp15
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, vcc_hi, 0xaf123456
+v_cvt_pk_norm_u16_f32 v5, vcc_hi, 0xaf123456
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
-v_cvt_pknorm_u16_f32 v5, ttmp15, src_scc
+v_cvt_pk_norm_u16_f32 v5, ttmp15, src_scc
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00]
-v_cvt_pknorm_u16_f32 v5, m0, 0.5
+v_cvt_pk_norm_u16_f32 v5, m0, 0.5
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00]
-v_cvt_pknorm_u16_f32 v5, exec_lo, -1
+v_cvt_pk_norm_u16_f32 v5, exec_lo, -1
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00]
-v_cvt_pknorm_u16_f32 v5, |exec_hi|, null
+v_cvt_pk_norm_u16_f32 v5, |exec_hi|, null
// GFX11: encoding: [0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, null, exec_lo
+v_cvt_pk_norm_u16_f32 v5, null, exec_lo
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, -1, exec_hi
+v_cvt_pk_norm_u16_f32 v5, -1, exec_hi
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00]
-v_cvt_pknorm_u16_f32 v5, 0.5, -m0
+v_cvt_pk_norm_u16_f32 v5, 0.5, -m0
// GFX11: encoding: [0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40]
-v_cvt_pknorm_u16_f32 v5, -src_scc, |vcc_lo|
+v_cvt_pk_norm_u16_f32 v5, -src_scc, |vcc_lo|
// GFX11: encoding: [0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20]
-v_cvt_pknorm_u16_f32 v255, -|0xaf123456|, -|vcc_hi|
+v_cvt_pk_norm_u16_f32 v255, -|0xaf123456|, -|vcc_hi|
// GFX11: encoding: [0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
v_div_fixup_f16 v5, v1, v2, s3
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
new file mode 100644
index 0000000000000..2dcc977f98323
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+
+v_cvt_pknorm_i16_f16 v5, v1, v2
+// GFX11: v_cvt_pk_norm_i16_f16 {{.*}} encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2
+// GFX11: v_cvt_pk_norm_u16_f16 {{.*}} encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
index dd8f465dc0a5c..92f194e63a33a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
@@ -1309,172 +1309,172 @@ v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 row_xmask:0 row_mask:0x1 bank_mask:0x3 b
v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x0d,0x30]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_mirror
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_mirror
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_half_mirror
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_shl:1
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:1
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_shl:15
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shl:15
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_shr:1
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:1
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_shr:15
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_shr:15
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_ror:1
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:1
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_ror:15
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_ror:15
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cvt_pknorm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-v_cvt_pknorm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
-v_cvt_pknorm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_mirror
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_mirror
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shl:1
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:1
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shl:15
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:15
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shr:1
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:1
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shr:15
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:15
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_ror:1
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:1
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_ror:15
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:15
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cvt_pknorm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-v_cvt_pknorm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
-v_cvt_pknorm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_mirror
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_mirror
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_half_mirror
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_shl:1
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:1
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_shl:15
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shl:15
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_shr:1
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:1
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_shr:15
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_shr:15
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_ror:1
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:1
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_ror:15
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_ror:15
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cvt_pknorm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-v_cvt_pknorm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
-v_cvt_pknorm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_mirror
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_mirror
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shl:1
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:1
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shl:15
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:15
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shr:1
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:1
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shr:15
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:15
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_ror:1
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:1
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_ror:15
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:15
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_cvt_pknorm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
+v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
-v_cvt_pknorm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
-v_cvt_pknorm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
v_div_fixup_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
index 5742817e63801..1fba5911276ef 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
@@ -672,52 +672,52 @@ v_cvt_pk_u8_f32_e64_dpp v5, v1, v2, 0.5 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: [0xff,0x01,0x26,0xd6,0xe9,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00]
-v_cvt_pknorm_i16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_i16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0x12,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_i16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x01,0x12,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+v_cvt_pk_norm_i16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: [0x05,0x02,0x12,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+v_cvt_pk_norm_i16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: [0xff,0x03,0x12,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
-v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: [0x05,0x02,0x21,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: [0xff,0x03,0x21,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
-v_cvt_pknorm_u16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_u16_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0x13,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_u16_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x01,0x13,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+v_cvt_pk_norm_u16_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: [0x05,0x02,0x13,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+v_cvt_pk_norm_u16_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: [0xff,0x03,0x13,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
-v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
+v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: [0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
+v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: [0x05,0x02,0x22,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
-v_cvt_pknorm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
+v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: [0xff,0x03,0x22,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
v_div_fixup_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
index 1db00580d789c..cc6c48a059c47 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
@@ -1344,94 +1344,94 @@
# GFX11: v_cvt_pk_u8_f32 v255, -|0xaf123456|, vcc_hi, null ; encoding: [0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf]
0xff,0x01,0x26,0xd6,0xff,0xd6,0xf0,0x21,0x56,0x34,0x12,0xaf
-# GFX11: v_cvt_pknorm_i16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00]
0x05,0x00,0x21,0xd7,0x01,0x05,0x02,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00]
0x05,0x00,0x21,0xd7,0xff,0xff,0x03,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00]
0x05,0x00,0x21,0xd7,0x01,0x04,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00]
0x05,0x00,0x21,0xd7,0x69,0xd2,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00]
0x05,0x00,0x21,0xd7,0x6a,0xf6,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
0x05,0x00,0x21,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
-# GFX11: v_cvt_pknorm_i16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00]
0x05,0x00,0x21,0xd7,0x7b,0xfa,0x01,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00]
0x05,0x00,0x21,0xd7,0x7d,0xe0,0x01,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00]
0x05,0x00,0x21,0xd7,0x7e,0x82,0x01,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00]
0x05,0x01,0x21,0xd7,0x7f,0xf8,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00]
0x05,0x00,0x21,0xd7,0x7c,0xfc,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00]
0x05,0x00,0x21,0xd7,0xc1,0xfe,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40]
0x05,0x00,0x21,0xd7,0xf0,0xfa,0x00,0x40
-# GFX11: v_cvt_pknorm_i16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20]
+# GFX11: v_cvt_pk_norm_i16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20]
0x05,0x02,0x21,0xd7,0xfd,0xd4,0x00,0x20
-# GFX11: v_cvt_pknorm_i16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+# GFX11: v_cvt_pk_norm_i16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
0xff,0x03,0x21,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
-# GFX11: v_cvt_pknorm_u16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00]
0x05,0x00,0x22,0xd7,0x01,0x05,0x02,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00]
0x05,0x00,0x22,0xd7,0xff,0xff,0x03,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00]
0x05,0x00,0x22,0xd7,0x01,0x04,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00]
0x05,0x00,0x22,0xd7,0x69,0xd2,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00]
0x05,0x00,0x22,0xd7,0x6a,0xf6,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
0x05,0x00,0x22,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf
-# GFX11: v_cvt_pknorm_u16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00]
0x05,0x00,0x22,0xd7,0x7b,0xfa,0x01,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00]
0x05,0x00,0x22,0xd7,0x7d,0xe0,0x01,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00]
0x05,0x00,0x22,0xd7,0x7e,0x82,0x01,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00]
0x05,0x01,0x22,0xd7,0x7f,0xf8,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00]
0x05,0x00,0x22,0xd7,0x7c,0xfc,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00]
0x05,0x00,0x22,0xd7,0xc1,0xfe,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40]
0x05,0x00,0x22,0xd7,0xf0,0xfa,0x00,0x40
-# GFX11: v_cvt_pknorm_u16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20]
+# GFX11: v_cvt_pk_norm_u16_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20]
0x05,0x02,0x22,0xd7,0xfd,0xd4,0x00,0x20
-# GFX11: v_cvt_pknorm_u16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
+# GFX11: v_cvt_pk_norm_u16_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf]
0xff,0x03,0x22,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf
# GFX11: v_div_fixup_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x54,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
index 3dd7727a3dabd..e9da1905f177f 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
@@ -1041,88 +1041,88 @@
# GFX11: v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x0d,0x30]
0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x0d,0x30
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30
# GFX11: v_fma_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
index 3f4f44a479fd5..f91216a7469c5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
@@ -573,28 +573,28 @@
# GFX11: v_cvt_pk_u8_f32_e64_dpp v255, -|v255|, v255, src_scc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x01,0x26,0xd6,0xea,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00]
0xff,0x01,0x26,0xd6,0xea,0xfe,0xf7,0x23,0xff,0x00,0x00,0x00
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x05,0x00,0x21,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
0x05,0x01,0x21,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x21,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x21,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
0x05,0x02,0x21,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# GFX11: v_cvt_pk_norm_i16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x21,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
0xff,0x03,0x21,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
0x05,0x00,0x22,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05]
0x05,0x01,0x22,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x22,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x22,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05]
0x05,0x02,0x22,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05
-# GFX11: v_cvt_pknorm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
+# GFX11: v_cvt_pk_norm_u16_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x03,0x22,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00]
0xff,0x03,0x22,0xd7,0xea,0xfe,0x03,0x60,0xff,0x00,0x00,0x00
# GFX11: v_fma_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x13,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
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