[PATCH] D143157: [AArch64] Add NZCV Def for TLSDESC_CALLSEQ

[Mirko Müller via Phabricator via llvm-commits]

MuellerMP updated this revision to Diff 494544.
MuellerMP added a comment.

Ran update_llc_test_checks on the test and added a comment to it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143157/new/

https://reviews.llvm.org/D143157

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll


Index: llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-tls-flags.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -relocation-model=pic -verify-machineinstrs %s -o - | FileCheck %s
+
+; TLSDESC resolver calling convention does not retain the flags register.
+; Check that a TLS descriptor call cannot be lowered in between a cmp and the use of flags.
+
+ at var = thread_local global i32 zeroinitializer
+ at test = global i32 zeroinitializer
+
+define i32 @test_thread_local() {
+; CHECK-LABEL: test_thread_local:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset w30, -16
+; CHECK-NEXT:    adrp x8, :got:test
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:test]
+; CHECK-NEXT:    adrp x0, :tlsdesc:var
+; CHECK-NEXT:    ldr x1, [x0, :tlsdesc_lo12:var]
+; CHECK-NEXT:    add x0, x0, :tlsdesc_lo12:var
+; CHECK-NEXT:    .tlsdesccall var
+; CHECK-NEXT:    blr x1
+; CHECK-NEXT:    mrs x9, TPIDR_EL0
+; CHECK-NEXT:    ldr w9, [x9, x0]
+; CHECK-NEXT:    cmp x8, #0
+; CHECK-NEXT:    cinc w0, w9, eq
+; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
+
+  %testval = load i32, ptr @test
+  %test = icmp eq ptr @test, null
+  %val = load i32, ptr @var
+  %result = zext i1 %test to i32
+  %result2 = add i32 %val, %result
+  ret i32 %result2
+
+}
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2612,7 +2612,7 @@
 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
 // FIXME: can "hasSideEffects be dropped?
 // This gets lowered to an instruction sequence which takes 16 bytes
-let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, Size = 16,
+let isCall = 1, Defs = [NZCV, LR, X0, X1], hasSideEffects = 1, Size = 16,
     isCodeGenOnly = 1 in
 def TLSDESC_CALLSEQ
     : Pseudo<(outs), (ins i64imm:$sym),


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