[llvm] 3a01b4a - AMDGPU: Regenerate test checks
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 2 18:50:34 PST 2023
Author: Matt Arsenault
Date: 2023-02-02T22:50:23-04:00
New Revision: 3a01b4a93df22bf4e0c5e49b756f92f96df3874c
URL: https://github.com/llvm/llvm-project/commit/3a01b4a93df22bf4e0c5e49b756f92f96df3874c
DIFF: https://github.com/llvm/llvm-project/commit/3a01b4a93df22bf4e0c5e49b756f92f96df3874c.diff
LOG: AMDGPU: Regenerate test checks
Use right prefix order to get merging.
Also drop -verify-machineinstrs and add -amdgpu-enable-delay-alu=0
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 712a15ebd230..e6c4bdd5bc2a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1,13 +1,14 @@
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7SELDAG,GFX7CHECK %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7GLISEL,GFX7CHECK %s
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8SELDAG,GFX8CHECK %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8GLISEL,GFX8CHECK %s
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9SELDAG,GFX9CHECK %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9GLISEL,GFX9CHECK %s
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10SELDAG,GFX10CHECK %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10GLISEL,GFX10CHECK %s
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11SELDAG,GFX11CHECK %s
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11GLISEL,GFX11CHECK %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7SELDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7GLISEL %s
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8SELDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8GLISEL %s
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9SELDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9GLISEL %s
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10SELDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10GLISEL %s
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11SELDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11GLISEL %s
define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX7SELDAG-LABEL: sgpr_isnan_f16:
@@ -83,7 +84,6 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0
; GFX11CHECK-NEXT: s_waitcnt lgkmcnt(0)
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; GFX11CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -144,31 +144,57 @@ define i1 @allflags_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, -1
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8CHECK-LABEL: allflags_f16:
-; GFX8CHECK: ; %bb.0:
-; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_mov_b32_e32 v0, {{(-)?}}1
-; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
+; GFX8SELDAG-LABEL: allflags_f16:
+; GFX8SELDAG: ; %bb.0:
+; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8SELDAG-NEXT: v_mov_b32_e32 v0, 1
+; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9CHECK-LABEL: allflags_f16:
-; GFX9CHECK: ; %bb.0:
-; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: v_mov_b32_e32 v0, {{(-)?}}1
-; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
+; GFX8GLISEL-LABEL: allflags_f16:
+; GFX8GLISEL: ; %bb.0:
+; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8GLISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10CHECK-LABEL: allflags_f16:
-; GFX10CHECK: ; %bb.0:
-; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10CHECK-NEXT: v_mov_b32_e32 v0, {{(-)?}}1
-; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
+; GFX9SELDAG-LABEL: allflags_f16:
+; GFX9SELDAG: ; %bb.0:
+; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, 1
+; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11CHECK-LABEL: allflags_f16:
-; GFX11CHECK: ; %bb.0:
-; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11CHECK-NEXT: v_mov_b32_e32 v0, {{(-)?}}1
-; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
+; GFX9GLISEL-LABEL: allflags_f16:
+; GFX9GLISEL: ; %bb.0:
+; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10SELDAG-LABEL: allflags_f16:
+; GFX10SELDAG: ; %bb.0:
+; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, 1
+; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10GLISEL-LABEL: allflags_f16:
+; GFX10GLISEL: ; %bb.0:
+; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10GLISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11SELDAG-LABEL: allflags_f16:
+; GFX11SELDAG: ; %bb.0:
+; GFX11SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11SELDAG-NEXT: v_mov_b32_e32 v0, 1
+; GFX11SELDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11GLISEL-LABEL: allflags_f16:
+; GFX11GLISEL: ; %bb.0:
+; GFX11GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11GLISEL-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11GLISEL-NEXT: v_mov_b32_e32 v0, -1
+; GFX11GLISEL-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1023) ; 0x3ff
ret i1 %1
}
@@ -227,7 +253,6 @@ define i1 @snan_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 1
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1) ; 0x001
@@ -282,7 +307,6 @@ define i1 @qnan_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 2
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 2) ; 0x002
@@ -337,7 +361,6 @@ define i1 @posinf_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x200
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 512) ; 0x200
@@ -390,7 +413,6 @@ define i1 @neginf_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 4
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 4) ; 0x004
@@ -457,7 +479,6 @@ define i1 @posnormal_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x100
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 256) ; 0x100
@@ -522,7 +543,6 @@ define i1 @negnormal_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 8
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 8) ; 0x008
@@ -580,7 +600,6 @@ define i1 @possubnormal_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x80
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 128) ; 0x080
@@ -644,7 +663,6 @@ define i1 @negsubnormal_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 16
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 16) ; 0x010
@@ -695,7 +713,6 @@ define i1 @poszero_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 64
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 64) ; 0x040
@@ -748,7 +765,6 @@ define i1 @negzero_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 32
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 32) ; 0x020
@@ -774,38 +790,37 @@ define i1 @posfinite_f16(half %x) nounwind {
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8SELDAG-LABEL: posfinite_f16:
-; GFX8SELDAG: ; %bb.0:
-; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, 0x1c0
-; GFX8SELDAG-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8CHECK-LABEL: posfinite_f16:
+; GFX8CHECK: ; %bb.0:
+; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
+; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
+; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9SELDAG-LABEL: posfinite_f16:
-; GFX9SELDAG: ; %bb.0:
-; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, 0x1c0
-; GFX9SELDAG-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9CHECK-LABEL: posfinite_f16:
+; GFX9CHECK: ; %bb.0:
+; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
+; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
+; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10SELDAG-LABEL: posfinite_f16:
-; GFX10SELDAG: ; %bb.0:
-; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1c0
-; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX10CHECK-LABEL: posfinite_f16:
+; GFX10CHECK: ; %bb.0:
+; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1c0
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11SELDAG-LABEL: posfinite_f16:
-; GFX11SELDAG: ; %bb.0:
-; GFX11SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11SELDAG-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1c0
-; GFX11SELDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
-; GFX11SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX11CHECK-LABEL: posfinite_f16:
+; GFX11CHECK: ; %bb.0:
+; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1c0
+; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 448) ; 0x1c0
ret i1 %1
}
@@ -864,7 +879,6 @@ define i1 @negfinite_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 56
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 56) ; 0x038
@@ -919,7 +933,6 @@ define i1 @isnan_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
@@ -994,10 +1007,8 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3) ; nan
@@ -1128,7 +1139,6 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11SELDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11SELDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v2, v2
; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
@@ -1142,14 +1152,11 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11GLISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v0, 3
-; GFX11GLISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v2, 3
-; GFX11GLISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v1, 3
; GFX11GLISEL-NEXT: v_mov_b32_e32 v1, v3
-; GFX11GLISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11GLISEL-NEXT: s_setpc_b64 s[30:31]
%1 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> %x, i32 3) ; nan
@@ -1234,19 +1241,19 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
;
; GFX9SELDAG-LABEL: isnan_v4f16:
; GFX9SELDAG: ; %bb.0:
-; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
-; GFX9SELDAG-NEXT: v_mov_b32_e32 v3, 3
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
-; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
-; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
-; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
-; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, v5
-; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v4
-; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
+; GFX9SELDAG-NEXT: v_mov_b32_e32 v3, 3
+; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
+; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, v5
+; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v4
+; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9GLISEL-LABEL: isnan_v4f16:
; GFX9GLISEL: ; %bb.0:
@@ -1266,20 +1273,20 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
;
; GFX10SELDAG-LABEL: isnan_v4f16:
; GFX10SELDAG: ; %bb.0:
-; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10SELDAG-NEXT: v_mov_b32_e32 v2, 3
-; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v0, 3
-; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
-; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s5, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
-; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
-; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, v4
-; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
-; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v1, 3
-; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v5
-; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
-; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10SELDAG-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v2, 3
+; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v0, 3
+; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
+; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s5, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, v4
+; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
+; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v1, 3
+; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v5
+; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
+; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10GLISEL-LABEL: isnan_v4f16:
; GFX10GLISEL: ; %bb.0:
@@ -1305,12 +1312,10 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v3, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v4, 3
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
@@ -1367,7 +1372,6 @@ define i1 @isnan_f16_strictfp(half %x) strictfp nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
@@ -1424,7 +1428,6 @@ define i1 @isinf_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 516) ; 0x204 = "inf"
@@ -1481,7 +1484,6 @@ define i1 @isfinite_f16(half %x) nounwind {
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1f8
-; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; 0x1f8 = "finite"
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