[PATCH] D143138: AMDGPU: Use module flag to get code object version at IR level

Thu Feb 2 16:01:46 PST 2023

cfang updated this revision to Diff 494458.
cfang marked an inline comment as done.
cfang added a comment.

Update based on Matt's comments:

1. Add a test case for out of range code object version;
2. Move code object version  into AMDGPUInformationCache
3. Pass code object version as an argument in MetadataStreamerMsgPackV3::getHSAKernelProps

4 remove unnecessary parens

The unreachable  code object version will be handled in a later patch, together with other considerations.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143138/new/

https://reviews.llvm.org/D143138

Files:
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
  llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
  llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
  llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
  llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
  llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
  llvm/test/CodeGen/AMDGPU/addrspacecast.ll
  llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-v3.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/elf-notes.ll
  llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
  llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
  llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll
  llvm/test/CodeGen/AMDGPU/hsa-default-device.ll
  llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
  llvm/test/CodeGen/AMDGPU/hsa-func.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-deduce-ro-arg.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ctor-dtor-list.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-heap-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-v3-asan.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-images-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-multigrid-sync-arg-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-queueptr-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-resource-usage-function-ordering.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-uniform-workgroup-size-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-workgroup-processor-mode-v5.ll
  llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll
  llvm/test/CodeGen/AMDGPU/hsa.ll
  llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
  llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
  llvm/test/CodeGen/AMDGPU/implicit-kernel-argument-alignment.ll
  llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/kernarg-size.ll
  llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
  llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
  llvm/test/CodeGen/AMDGPU/lds-alignment.ll
  llvm/test/CodeGen/AMDGPU/lds-size.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
  llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
  llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
  llvm/test/CodeGen/AMDGPU/nop-data.ll
  llvm/test/CodeGen/AMDGPU/private-element-size.ll
  llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll
  llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
  llvm/test/CodeGen/AMDGPU/recursion.ll
  llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
  llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
  llvm/test/CodeGen/AMDGPU/tid-code-object-v2-backwards-compatibility.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
  llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll
  llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
  llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
  llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
  llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
  llvm/test/CodeGen/AMDGPU/trap-abis.ll
  llvm/test/CodeGen/AMDGPU/trap.ll
  llvm/test/CodeGen/AMDGPU/unsupported-code-object-version.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll

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