[PATCH] D143220: [RISCV] Remove side effects from vsetvli intrinsics.

[Craig Topper via Phabricator via llvm-commits]

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Delete the opt intrinsics since they are now identical.

I left the side effects due to user expectations about how these
interact with things like inline assembly or function calls. Or
that they wouldn't be hoisted. I think we should look at other
ways to address thoughs.

If I could, I'd rename them these somehow to distance them from
the vsetvli instruction. In some sense they only query the VL for
a particular SEW and LMUL. They don't guarantee a vsetvli
instruction will be emitted.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143220

Files:
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Analysis/ValueTracking.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
  llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
  llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll

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