[PATCH] D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

[Philipp Tomsich via Phabricator via llvm-commits]

philipp.tomsich updated this revision to Diff 494387.
philipp.tomsich added a comment.

- wire up to existing optimisations in RISCVISelLowering.cpp
- rewrite RISCVTargetLowering::hasBitTest() to differentiate between immediate and non-immediate cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143036/new/

https://reviews.llvm.org/D143036

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32xtheadbs.ll
  llvm/test/CodeGen/RISCV/rv64xtheadbs.ll
  llvm/test/MC/RISCV/rv32xtheadbs-invalid.s
  llvm/test/MC/RISCV/rv32xtheadbs-valid.s
  llvm/test/MC/RISCV/rv64xtheadbs-invalid.s

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