[PATCH] D142348: [RISCV][Docs] Document code generation for vector extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I only did a quick review.



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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:162
+
+The specification requires that ``VLEN`` must be a minimum of 128 bits, and LLVM supports only ``ELEN=32`` or ``ELEN=64``, so ``vscale`` is defined as ``VLEN/64``.
+This makes the LLVM IR types stable between the two ``ELEN`` s considered, i.e. every LLVM IR scalable vector type has exactly one corresponding pair of element type and LMUL, and vice-versa.
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VLEN is not limited to 128 bits. It can be 32 or 64.


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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:185
+
+One downside of this design is that doesn’t allow vectors of i128 (this is, ELEN=128). In that case vscale would have to be 1/2 under :math:`\text{LMUL}=1`. This type (and its fp counterpart float128) are not that common and in case of extreme necessity types for :math:`\text{LMUL}=2` could be used instead.
+
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This mapping also prevents the value of vscale from being examined if ELEN and VLEN are both 32.


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Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:293
+To assist with this, an intermediate layer of nodes that take an explicit ``VL`` operand is used.
+The nodes and their patterns are defined in ``RISCVInstrInfoVVLPatterns.td``.
+
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This file is also used VP intrinsics for scalable vectors.


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