[PATCH] D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32xtheadbs.ll:7
+
+define i32 @bexti_i32(i32 %a) nounwind {
+; RV32I-LABEL: bexti_i32:
----------------
Rename these tests from `bexti` to `th_tst`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143036/new/

https://reviews.llvm.org/D143036