[llvm] c6795b1 - Use ArrayRef instead of raw pointers. NFC
Serge Pavlov via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 1 21:55:59 PST 2023
Author: Serge Pavlov
Date: 2023-02-02T12:53:49+07:00
New Revision: c6795b1d37cee586d9b98dade64432f8f6bd004b
URL: https://github.com/llvm/llvm-project/commit/c6795b1d37cee586d9b98dade64432f8f6bd004b
DIFF: https://github.com/llvm/llvm-project/commit/c6795b1d37cee586d9b98dade64432f8f6bd004b.diff
LOG: Use ArrayRef instead of raw pointers. NFC
Change signature of TargetLowering::getRoundingControlRegisters so that
it returns ArrayRef, not plain pointer.
Differential Revision: https://reviews.llvm.org/D143049
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4374f7e294cda..9ad82ab05874a 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4490,8 +4490,8 @@ class TargetLowering : public TargetLoweringBase {
/// Returns a 0 terminated array of rounding control registers that can be
/// attached into strict FP call.
- virtual const MCPhysReg *getRoundingControlRegisters() const {
- return nullptr;
+ virtual ArrayRef<MCPhysReg> getRoundingControlRegisters() const {
+ return ArrayRef<MCPhysReg>();
}
/// This callback is used to prepare for a volatile or atomic load.
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 5cd5de71b9d0b..ef8da41d11c9c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -1163,10 +1163,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
// Add rounding control registers as implicit def for function call.
if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
- const MCPhysReg *RCRegs = TLI->getRoundingControlRegisters();
- if (RCRegs)
- for (; *RCRegs; ++RCRegs)
- UsedRegs.push_back(*RCRegs);
+ ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
+ for (MCPhysReg Reg : RCRegs)
+ UsedRegs.push_back(Reg);
}
// Finally mark unused registers as dead.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 72e99b3e176e1..fe356cbfc00e0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14946,8 +14946,8 @@ AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
return ScratchRegs;
}
-const MCPhysReg *AArch64TargetLowering::getRoundingControlRegisters() const {
- static const MCPhysReg RCRegs[] = {AArch64::FPCR, 0};
+ArrayRef<MCPhysReg> AArch64TargetLowering::getRoundingControlRegisters() const {
+ static const MCPhysReg RCRegs[] = {AArch64::FPCR};
return RCRegs;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 7544a0c5b21e9..171c31001a00f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -670,7 +670,7 @@ class AArch64TargetLowering : public TargetLowering {
CodeGenOpt::Level OptLevel) const override;
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
- const MCPhysReg *getRoundingControlRegisters() const override;
+ ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
/// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool isDesirableToCommuteWithShift(const SDNode *N,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8311a5a12032a..415064433089c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3097,10 +3097,10 @@ const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
return ScratchRegs;
}
-const MCPhysReg *X86TargetLowering::getRoundingControlRegisters() const {
+ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
// FIXME: We should def X86::FPCW for x87 as well. But it affects a lot of lit
// tests at the moment, which is not what we expected.
- static const MCPhysReg RCRegs[] = { X86::MXCSR, 0 };
+ static const MCPhysReg RCRegs[] = {X86::MXCSR};
return RCRegs;
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 7f56d8da004ec..c41b5fdbeca88 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1702,7 +1702,7 @@ namespace llvm {
LLVMContext &Context) const override;
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
- const MCPhysReg *getRoundingControlRegisters() const override;
+ ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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