[PATCH] D141712: [GVN] Improve PRE on load instructions

[Arthur Eubanks via Phabricator via llvm-commits]

aeubanks added a comment.

slightly modified from one of the test cases:

  declare i1 @foo()
  declare void @maybethrow() readnone
  
  ; %v3 is partially redundant, bb3 has multiple predecessors coming through
  ; critical edges. The other successors of those predecessors have same loads.
  ; We can move all loads into predecessors.
  
  define void @test17(ptr %p1, ptr %p2, ptr %p3, ptr %p4) {
  entry:
    %v1 = load i64, ptr %p1, align 8
    %cond1 = icmp sgt i64 %v1, 200
    br i1 %cond1, label %bb200, label %bb1
  
  bb1:
    %cond2 = icmp sgt i64 %v1, 100
    br i1 %cond2, label %bb100, label %bb2
  
  bb2:
    %v2 = add nsw i64 %v1, 1
    store i64 %v2, ptr %p1, align 8
    br label %bb3
  
  bb3:
    %v3 = load i64, ptr %p1, align 8
    store i64 %v3, ptr %p2, align 8
    ret void
  
  bb100:
    %cond3 = call i1 @foo()
    br i1 %cond3, label %bb3, label %bb101
  
  bb101:
    %v4 = load i64, ptr %p1, align 8
    store i64 %v4, ptr %p3, align 8
    ret void
  
  bb200:
    %cond4 = call i1 @foo()
    br i1 %cond4, label %bb3, label %bb201
  
  bb201:
    %_ = call i1 @maybethrow()
    %v5 = load i64, ptr %p1, align 8
    store i64 %v5, ptr %p4, align 8
    ret void
  }

becomes

  declare i1 @foo()
  
  ; Function Attrs: memory(none)
  declare void @maybethrow() #0
  
  define void @test17(ptr %p1, ptr %p2, ptr %p3, ptr %p4) {
  entry:
    %v1 = load i64, ptr %p1, align 8
    %cond1 = icmp sgt i64 %v1, 200
    br i1 %cond1, label %bb200, label %bb1
  
  bb1:                                              ; preds = %entry
    %cond2 = icmp sgt i64 %v1, 100
    br i1 %cond2, label %bb100, label %bb2
  
  bb2:                                              ; preds = %bb1
    %v2 = add nsw i64 %v1, 1
    store i64 %v2, ptr %p1, align 8
    br label %bb3
  
  bb3:                                              ; preds = %bb200, %bb100, %bb2
    %v3 = phi i64 [ %v3.pre, %bb200 ], [ %v3.pre1, %bb100 ], [ %v2, %bb2 ]
    store i64 %v3, ptr %p2, align 8
    ret void
  
  bb100:                                            ; preds = %bb1
    %cond3 = call i1 @foo()
    %v3.pre1 = load i64, ptr %p1, align 8
    br i1 %cond3, label %bb3, label %bb101
  
  bb101:                                            ; preds = %bb100
    store i64 %v3.pre1, ptr %p3, align 8
    ret void
  
  bb200:                                            ; preds = %entry
    %cond4 = call i1 @foo()
    %v3.pre = load i64, ptr %p1, align 8
    br i1 %cond4, label %bb3, label %bb201
  
  bb201:                                            ; preds = %bb200
    %_ = call i1 @maybethrow()
    store i64 %v3.pre, ptr %p4, align 8
    ret void
  }
  
  attributes #0 = { memory(none) }

`%v5` is hoisted above `call @maybethrow()`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141712/new/

https://reviews.llvm.org/D141712