[PATCH] D143106: [SDAG] fix miscompiles caused by using ValueTracking matchSelectPattern to create FMINIMUM/FMAXIMUM

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
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ValueTracking attempts to match compare+select patterns to FP min/max operations, but it was created before the newer IEEE-754-2019 minimum/maximum ops were defined. Ie, `matchSelectPattern()` does not account for the -0.0/+0.0 behavior that is specified in the newer standard.

FMINIMUM/FMAXIMUM nodes were created to map to the newer standard:

  /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
  /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
  /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.

We could adjust ValueTracking to deal with signed zero, but it seems like a moot point given the divergent NaN behavior discussed in D143056 <https://reviews.llvm.org/D143056>, so just delete this possibility to avoid bugs when converting IR to SDAG.


https://reviews.llvm.org/D143106

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
  llvm/test/CodeGen/AArch64/tbl-loops.ll
  llvm/test/CodeGen/ARM/neon_minmax.ll
  llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
  llvm/test/CodeGen/SystemZ/vec-max-05.ll
  llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll
  llvm/test/CodeGen/SystemZ/vec-min-05.ll
  llvm/test/CodeGen/WebAssembly/f32.ll
  llvm/test/CodeGen/WebAssembly/f64.ll
  llvm/test/CodeGen/WebAssembly/simd-arith.ll

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