[PATCH] D140542: [MachineCombiner] Support local strategy for traces

Wed Feb 1 08:06:01 PST 2023

spatel added a comment.

In D140542#4096373 <https://reviews.llvm.org/D140542#4096373>, @asi-sc wrote:

> In D140542#4090627 <https://reviews.llvm.org/D140542#4090627>, @spatel wrote:
>
>> But does that mean the test difference that you are showing will also occur for SiFive7, Syntacore SCR1, and/or Rocket with this patch? If so, can you add a RUN line to the test file like that?
>
> I added one more test for Syntacore-SCR1 and SiFive-u74. It shows the desired reassociation when the local strategy is used. Reassociated in this way instructions demonstrate better ILP.
> One thing we should understand is that RISC-V reassociation patterns for machine combiner are not really interesting for Syntacore SCR1 as it is a single-issue CPU and doesn't support FP extensions. However, when locally strategy is used, resulted asm is not worse for Syntacore-SCR1 and slightly better for SiFive-u74 (which is dual-issue).

Thanks - I don't know anything about RISC-V chips, so I'm deferring to others on that.

The asm diffs in existing test files show that we are affecting the default behavior of RISC-V compiles, right? If those are considered neutral or improvements, then I think this is good to go.

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https://reviews.llvm.org/D140542