[llvm] c4e38fa - [AArch64] Mark function calls as possibly changing FPCR

[Serge Pavlov via llvm-commits]

Author: Serge Pavlov
Date: 2023-02-01T12:06:51+07:00
New Revision: c4e38fadfa2a615467a8c9071f12edc4cdce5eb8

URL: https://github.com/llvm/llvm-project/commit/c4e38fadfa2a615467a8c9071f12edc4cdce5eb8
DIFF: https://github.com/llvm/llvm-project/commit/c4e38fadfa2a615467a8c9071f12edc4cdce5eb8.diff

LOG: [AArch64] Mark function calls as possibly changing FPCR

This patch does the same changes as D111433 for PowerPC and D139549 for
X86, - in the strictfp function all calls are marked as implicit defs of
FPCR. It prevents from moving FP operations across function calls, which
may change rounding mode, as fesetround does.

Differential Revision: https://reviews.llvm.org/D143001

Added: 
    llvm/test/CodeGen/AArch64/strict-fp-func.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/lib/Target/AArch64/AArch64ISelLowering.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ca6f1aa202918..72e99b3e176e1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -14946,6 +14946,11 @@ AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
   return ScratchRegs;
 }
 
+const MCPhysReg *AArch64TargetLowering::getRoundingControlRegisters() const {
+  static const MCPhysReg RCRegs[] = {AArch64::FPCR, 0};
+  return RCRegs;
+}
+
 bool
 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
                                                      CombineLevel Level) const {

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 92619f7e4c5a3..7544a0c5b21e9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -670,6 +670,7 @@ class AArch64TargetLowering : public TargetLowering {
                                      CodeGenOpt::Level OptLevel) const override;
 
   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
+  const MCPhysReg *getRoundingControlRegisters() const override;
 
   /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
   bool isDesirableToCommuteWithShift(const SDNode *N,

diff  --git a/llvm/test/CodeGen/AArch64/strict-fp-func.ll b/llvm/test/CodeGen/AArch64/strict-fp-func.ll
new file mode 100644
index 0000000000000..198d4fdea6831
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/strict-fp-func.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple aarch64-none-linux-gnu -stop-after=finalize-isel %s -o - | FileCheck %s
+
+define float @func_02(float %x, float %y) strictfp nounwind {
+  %call = call float @func_01(float %x) strictfp
+  %res = call float @llvm.experimental.constrained.fadd.f32(float %call, float %y, metadata !"round.dynamic", metadata !"fpexcept.ignore") strictfp
+  ret float %res
+}
+; CHECK-LABEL: name: func_02
+; CHECK:       BL @func_01, {{.*}}, implicit-def $fpcr
+
+
+declare float @func_01(float)
+declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)