[PATCH] D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:799
 
     // If C2 is (1 << ShAmt) use bexti if possible.
+    if ((Subtarget->hasStdExtZbs() || Subtarget->hasVendorXTHeadBs()) &&
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Update comment to include th.tst


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:930
                       cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32;
           // Also Skip if we can use bexti.
           Skip |= Subtarget->hasStdExtZbs() && Leading == XLen - 1;
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Update comment


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  https://reviews.llvm.org/D143036/new/

https://reviews.llvm.org/D143036