[llvm] 2a45d06 - [GlobalISel] Don't combine instructions with unknown type in hoist_logic_op_with_same_opcode_hands.

[Vladislav Dzhidzhoev via llvm-commits]

Author: Vladislav Dzhidzhoev
Date: 2023-02-01T00:54:15+01:00
New Revision: 2a45d061ef81e9af7f61193691b1537b99898494

URL: https://github.com/llvm/llvm-project/commit/2a45d061ef81e9af7f61193691b1537b99898494
DIFF: https://github.com/llvm/llvm-project/commit/2a45d061ef81e9af7f61193691b1537b99898494.diff

LOG: [GlobalISel] Don't combine instructions with unknown type in hoist_logic_op_with_same_opcode_hands.

This fixes failure for some LLVM IR.

Differential Revision: https://reviews.llvm.org/D142791

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index bbb7c7c58ea15..7b85f2e9510b9 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2750,7 +2750,7 @@ bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
   Register Y = RightHandInst->getOperand(1).getReg();
   LLT XTy = MRI.getType(X);
   LLT YTy = MRI.getType(Y);
-  if (XTy != YTy)
+  if (!XTy.isValid() || XTy != YTy)
     return false;
   if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}}))
     return false;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
index b05bd923e34df..0c624d7cc224d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-hoist-same-hands.mir
@@ -58,3 +58,20 @@ body:             |
     %logic_op:_(s64) = G_OR %hand1, %hand2
     $x0 = COPY %logic_op(s64)
     RET_ReallyLR implicit $x0
+
+...
+---
+name:            dont_combine_physreg
+tracksRegLiveness: true
+legalized: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+    ; Post-legalization, we must not crash here.
+    ;
+    ; CHECK-LABEL: name: dont_combine_physreg
+    %x:_(s32) = COPY $w0
+    %y:_(s32) = COPY $w1
+    %logic_op:_(s32) = G_OR %x, %y
+    $w0 = COPY %logic_op(s32)
+    RET_ReallyLR implicit $w0