[llvm] 6a1b2d0 - [RISCV] Handle FRMArg as an optional operand instead of using InstAliases.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 31 09:08:23 PST 2023
Author: Craig Topper
Date: 2023-01-31T09:08:13-08:00
New Revision: 6a1b2d04288296606767bce08b3229e0e72e0100
URL: https://github.com/llvm/llvm-project/commit/6a1b2d04288296606767bce08b3229e0e72e0100
DIFF: https://github.com/llvm/llvm-project/commit/6a1b2d04288296606767bce08b3229e0e72e0100.diff
LOG: [RISCV] Handle FRMArg as an optional operand instead of using InstAliases.
Instead of having InstAliases without operand. Use the optional
operand infrastructure.
Still use the PrintAliases/NoAlias controls to determine if we
print "dyn" or not.
Differential Revision: https://reviews.llvm.org/D142959
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 8525b5fef599a..b43cbe4744c1d 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -224,6 +224,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
}
std::unique_ptr<RISCVOperand> defaultMaskRegOp() const;
+ std::unique_ptr<RISCVOperand> defaultFRMArgOp() const;
public:
enum RISCVMatchResultTy {
@@ -2639,6 +2640,11 @@ std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {
llvm::SMLoc(), isRV64());
}
+std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultFRMArgOp() const {
+ return RISCVOperand::createFRMArg(RISCVFPRndMode::RoundingMode::DYN,
+ llvm::SMLoc());
+}
+
bool RISCVAsmParser::validateInstruction(MCInst &Inst,
OperandVector &Operands) {
if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index a4fbba7ae1e98..bae812eca595f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -149,7 +149,9 @@ void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
auto FRMArg =
static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
- O << RISCVFPRndMode::roundingModeToString(FRMArg);
+ if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
+ return;
+ O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
}
void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 7863120dc16e6..cd6ff9e62b5ea 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -108,11 +108,6 @@ defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", DINX>;
defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", DINX>;
}
-defm : FPFMADynFrmAlias_m<FMADD_D, "fmadd.d", DINX>;
-defm : FPFMADynFrmAlias_m<FMSUB_D, "fmsub.d", DINX>;
-defm : FPFMADynFrmAlias_m<FNMSUB_D, "fnmsub.d", DINX>;
-defm : FPFMADynFrmAlias_m<FNMADD_D, "fnmadd.d", DINX>;
-
let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in {
defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX, /*Commutable*/1>;
defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>;
@@ -123,14 +118,8 @@ defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", DINX, /*Commutable*/1>;
let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in
defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", DINX>;
-defm : FPALUDynFrmAlias_m<FADD_D, "fadd.d", DINX>;
-defm : FPALUDynFrmAlias_m<FSUB_D, "fsub.d", DINX>;
-defm : FPALUDynFrmAlias_m<FMUL_D, "fmul.d", DINX>;
-defm : FPALUDynFrmAlias_m<FDIV_D, "fdiv.d", DINX>;
-
defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, DDINX, "fsqrt.d">,
Sched<[WriteFSqrt64, ReadFSqrt64]>;
-defm : FPUnaryOpDynFrmAlias_m<FSQRT_D, "fsqrt.d", DDINX>;
let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],
mayRaiseFPException = 0 in {
@@ -146,7 +135,6 @@ defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", DINX, /*Commutable*/1>;
defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, FDINX, "fcvt.s.d">,
Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_S_D, "fcvt.s.d", FDINX>;
defm FCVT_D_S : FPUnaryOp_r_m<0b0100001, 0b00000, 0b000, DFINX, "fcvt.d.s">,
Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
@@ -163,12 +151,10 @@ defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, XDINX, "fclass.d">,
let IsSignExtendingOpW = 1 in
defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, XDINX, "fcvt.w.d">,
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_W_D, "fcvt.w.d", XDINX>;
let IsSignExtendingOpW = 1 in
defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, XDINX, "fcvt.wu.d">,
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_D, "fcvt.wu.d", XDINX>;
defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, DXINX, "fcvt.d.w">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
@@ -178,11 +164,9 @@ defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, DXINX, "fcvt.d.wu">,
defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDIN64X, "fcvt.l.d">,
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_L_D, "fcvt.l.d", XDIN64X>;
defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDIN64X, "fcvt.lu.d">,
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_D, "fcvt.lu.d", XDIN64X>;
let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
@@ -190,11 +174,9 @@ def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXIN64X, "fcvt.d.l">,
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_D_L, "fcvt.d.l", DXIN64X>;
defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXIN64X, "fcvt.d.lu">,
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_D_LU, "fcvt.d.lu", DXIN64X>;
let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 344a3ae173a41..fe0d5a4306734 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -141,6 +141,8 @@ def FRMArg : AsmOperandClass {
let Name = "FRMArg";
let RenderMethod = "addFRMArgOperands";
let ParserMethod = "parseFRMArg";
+ let IsOptional = 1;
+ let DefaultMethod = "defaultFRMArgOp";
}
def frmarg : Operand<XLenVT> {
@@ -175,7 +177,7 @@ class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
DAGOperand rty>
: RVInstR4Frm<funct2, opcode, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
- opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">;
+ opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, bits<2> funct2,
string opcodestr, list<ExtInfo_r> Exts> {
@@ -184,18 +186,6 @@ multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, bits<2> funct2,
def Ext.Suffix : FPFMA_rrr_frm<opcode, funct2, opcodestr, Ext.Reg>;
}
-class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr,
- DAGOperand rty>
- : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
- (Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>;
-multiclass FPFMADynFrmAlias_m<FPFMA_rrr_frm Inst, string OpcodeStr,
- list<ExtInfo_r> Exts> {
- foreach Ext = Exts in
- let Predicates = Ext.Predicates in
- def : FPFMADynFrmAlias<!cast<FPFMA_rrr_frm>(Inst#Ext.Suffix), OpcodeStr,
- Ext.Reg>;
-}
-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
DAGOperand rty, bit Commutable>
@@ -216,7 +206,7 @@ class FPALU_rr_frm<bits<7> funct7, string opcodestr, DAGOperand rty,
bit Commutable>
: RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
- "$rd, $rs1, $rs2, $frm"> {
+ "$rd, $rs1, $rs2$frm"> {
let isCommutable = Commutable;
}
multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr,
@@ -226,18 +216,6 @@ multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr,
def Ext.Suffix : FPALU_rr_frm<funct7, opcodestr, Ext.Reg, Commutable>;
}
-class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr,
- DAGOperand rty>
- : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
- (Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>;
-multiclass FPALUDynFrmAlias_m<FPALU_rr_frm Inst, string OpcodeStr,
- list<ExtInfo_r> Exts> {
- foreach Ext = Exts in
- let Predicates = Ext.Predicates in
- def : FPALUDynFrmAlias<!cast<FPALU_rr_frm>(Inst#Ext.Suffix), OpcodeStr,
- Ext.Reg>;
-}
-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
DAGOperand rdty, DAGOperand rs1ty, string opcodestr>
@@ -259,7 +237,7 @@ class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
DAGOperand rs1ty, string opcodestr>
: RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
(ins rs1ty:$rs1, frmarg:$frm), opcodestr,
- "$rd, $rs1, $frm"> {
+ "$rd, $rs1$frm"> {
let rs2 = rs2val;
}
multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val,
@@ -270,18 +248,6 @@ multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val,
opcodestr>;
}
-class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
- DAGOperand rdty, DAGOperand rs1ty>
- : InstAlias<OpcodeStr#" $rd, $rs1",
- (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
-multiclass FPUnaryOpDynFrmAlias_m<FPUnaryOp_r_frm Inst, string OpcodeStr,
- list<ExtInfo_rr> Exts> {
- foreach Ext = Exts in
- let Predicates = Ext.Predicates in
- def : FPUnaryOpDynFrmAlias<!cast<FPUnaryOp_r_frm>(Inst#Ext.Suffix),
- OpcodeStr, Ext.RdTy, Ext.Rs1Ty>;
-}
-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
IsSignExtendingOpW = 1 in
class FPCmp_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
@@ -327,11 +293,6 @@ defm FNMSUB_S : FPFMA_rrr_frm_m<OPC_NMSUB, 0b00, "fnmsub.s", FINX>;
defm FNMADD_S : FPFMA_rrr_frm_m<OPC_NMADD, 0b00, "fnmadd.s", FINX>;
}
-defm : FPFMADynFrmAlias_m<FMADD_S, "fmadd.s", FINX>;
-defm : FPFMADynFrmAlias_m<FMSUB_S, "fmsub.s", FINX>;
-defm : FPFMADynFrmAlias_m<FNMSUB_S, "fnmsub.s", FINX>;
-defm : FPFMADynFrmAlias_m<FNMADD_S, "fnmadd.s", FINX>;
-
let SchedRW = [WriteFAdd32, ReadFAdd32, ReadFAdd32] in {
defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX, /*Commutable*/1>;
defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>;
@@ -342,14 +303,8 @@ defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", FINX, /*Commutable*/1>;
let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in
defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", FINX>;
-defm : FPALUDynFrmAlias_m<FADD_S, "fadd.s", FINX>;
-defm : FPALUDynFrmAlias_m<FSUB_S, "fsub.s", FINX>;
-defm : FPALUDynFrmAlias_m<FMUL_S, "fmul.s", FINX>;
-defm : FPALUDynFrmAlias_m<FDIV_S, "fdiv.s", FINX>;
-
defm FSQRT_S : FPUnaryOp_r_frm_m<0b0101100, 0b00000, FFINX, "fsqrt.s">,
Sched<[WriteFSqrt32, ReadFSqrt32]>;
-defm : FPUnaryOpDynFrmAlias_m<FSQRT_S, "fsqrt.s", FFINX>;
let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32],
mayRaiseFPException = 0 in {
@@ -366,12 +321,10 @@ defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", FINX, /*Commutable*/1>;
let IsSignExtendingOpW = 1 in
defm FCVT_W_S : FPUnaryOp_r_frm_m<0b1100000, 0b00000, XFINX, "fcvt.w.s">,
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_W_S, "fcvt.w.s", XFINX>;
let IsSignExtendingOpW = 1 in
defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, XFINX, "fcvt.wu.s">,
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_S, "fcvt.wu.s", XFINX>;
let Predicates = [HasStdExtF], mayRaiseFPException = 0,
IsSignExtendingOpW = 1 in
@@ -390,11 +343,9 @@ defm FCLASS_S : FPUnaryOp_r_m<0b1110000, 0b00000, 0b001, XFINX, "fclass.s">,
defm FCVT_S_W : FPUnaryOp_r_frm_m<0b1101000, 0b00000, FXINX, "fcvt.s.w">,
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_S_W, "fcvt.s.w", FXINX>;
defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">,
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_S_WU, "fcvt.s.wu", FXINX>;
let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
@@ -402,19 +353,15 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">,
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_L_S, "fcvt.l.s", XFIN64X>;
defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFIN64X, "fcvt.lu.s">,
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_S, "fcvt.lu.s", XFIN64X>;
defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXIN64X, "fcvt.s.l">,
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_S_L, "fcvt.s.l", FXIN64X>;
defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXIN64X, "fcvt.s.lu">,
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 914d39c583d78..82c65667db98e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -103,11 +103,6 @@ defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", HINX>;
defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", HINX>;
}
-defm : FPFMADynFrmAlias_m<FMADD_H, "fmadd.h", HINX>;
-defm : FPFMADynFrmAlias_m<FMSUB_H, "fmsub.h", HINX>;
-defm : FPFMADynFrmAlias_m<FNMSUB_H, "fnmsub.h", HINX>;
-defm : FPFMADynFrmAlias_m<FNMADD_H, "fnmadd.h", HINX>;
-
let SchedRW = [WriteFAdd16, ReadFAdd16, ReadFAdd16] in {
defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX, /*Commutable*/1>;
defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>;
@@ -118,14 +113,8 @@ defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", HINX, /*Commutable*/1>;
let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in
defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", HINX>;
-defm : FPALUDynFrmAlias_m<FADD_H, "fadd.h", HINX>;
-defm : FPALUDynFrmAlias_m<FSUB_H, "fsub.h", HINX>;
-defm : FPALUDynFrmAlias_m<FMUL_H, "fmul.h", HINX>;
-defm : FPALUDynFrmAlias_m<FDIV_H, "fdiv.h", HINX>;
-
defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, HHINX, "fsqrt.h">,
Sched<[WriteFSqrt16, ReadFSqrt16]>;
-defm : FPUnaryOpDynFrmAlias_m<FSQRT_H, "fsqrt.h", HHINX>;
let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16],
mayRaiseFPException = 0 in {
@@ -142,24 +131,19 @@ defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", HINX, /*Commutable*/1>;
let IsSignExtendingOpW = 1 in
defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, XHINX, "fcvt.w.h">,
Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_W_H, "fcvt.w.h", XHINX>;
let IsSignExtendingOpW = 1 in
defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, XHINX, "fcvt.wu.h">,
Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_H, "fcvt.wu.h", XHINX>;
defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, HXINX, "fcvt.h.w">,
Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_W, "fcvt.h.w", HXINX>;
defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, HXINX, "fcvt.h.wu">,
Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_WU, "fcvt.h.wu", HXINX>;
defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, HFINXmin, "fcvt.h.s">,
Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_S, "fcvt.h.s", HFINXmin>;
defm FCVT_S_H : FPUnaryOp_r_m<0b0100000, 0b00010, 0b000, FHINXmin, "fcvt.s.h">,
Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
@@ -186,23 +170,18 @@ defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, XHINX, "fclass.h">,
defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHIN64X, "fcvt.l.h">,
Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_L_H, "fcvt.l.h", XHIN64X>;
defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHIN64X, "fcvt.lu.h">,
Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_H, "fcvt.lu.h", XHIN64X>;
defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXIN64X, "fcvt.h.l">,
Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_L, "fcvt.h.l", HXIN64X>;
defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXIN64X, "fcvt.h.lu">,
Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_LU, "fcvt.h.lu", HXIN64X>;
defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, HDINXmin, "fcvt.h.d">,
Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>;
-defm : FPUnaryOpDynFrmAlias_m<FCVT_H_D, "fcvt.h.d", HDINXmin>;
defm FCVT_D_H : FPUnaryOp_r_m<0b0100001, 0b00010, 0b000, DHINXmin, "fcvt.d.h">,
Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>;
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