[PATCH] D141595: [AArch64][SME]: Add missing Ops that need custom-lowering in streaming mode.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Hi @hassnaa-arm, it seems there is some missing test coverage for some of the operations, which wasn't that easy to spot because this patch is quite big. It might help to split up this patch into smaller patches so that at least the sign-extend-inreg changes are in a separate patch, since it touches a number of test files.

It might also help to split out some of the others changes:

1. selects (since there are code changes to the LowerSELECT)
2. fp extends  (since there are code changes to the LowerFP_EXTEND)

You could choose to keep this patch for the bitreverse/bswap/vecreduce/splice/cttz (with added tests)



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1718
   setOperationAction(ISD::ANY_EXTEND, VT, Custom);
+  setOperationAction(ISD::BITREVERSE, VT, Custom);
+  setOperationAction(ISD::BSWAP, VT, Custom);
----------------
There are tests missing for bitreverse.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1724
   setOperationAction(ISD::CTPOP, VT, Custom);
+  setOperationAction(ISD::CTTZ, VT, Custom);
   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
----------------
There are tests missing for CTTZ


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1777
   setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
+  setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
   setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
----------------
There are tests missing in this patch for the vecreduce_* operations.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1789
   setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+  setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
+  setOperationAction(ISD::VSELECT, VT, Custom);
----------------
there are tests missing for vector_splice.


================
Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll:19
 ; CHECK-NEXT:    ptrue p0.h, vl4
-; CHECK-NEXT:    lsl z0.h, p0/m, z0.h, #8
-; CHECK-NEXT:    lsl z1.h, p0/m, z1.h, #8
-; CHECK-NEXT:    asr z0.h, p0/m, z0.h, #8
-; CHECK-NEXT:    asr z1.h, p0/m, z1.h, #8
+; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
+; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
----------------
I guess this change is caused by the sign-extend-inreg, maybe it's worth pulling that out into a separate patch?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141595/new/

https://reviews.llvm.org/D141595