[PATCH] D141693: [AArch64] turn extended vecreduce bigger than v16i8 into udot/sdot

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks for the updates. This looks very general now. I you agree with the comment about the offset, then this LGTM with that change.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15287
+      DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, A.getOperand(0),
+                  DAG.getConstant(I * 8, DL, MVT::i64));
+  SDValue Vec8Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, B,
----------------
zjaffal wrote:
> dmgreen wrote:
> > -> `I * 16`
> this is for extracting the v8 chuck I think it should be 8 not 16
I was thinking this should be 16 because we have extracted `I` lots of v16 chunk above, and so should be going that far into the original vector. For example with 24x case should be getting this from offset `16` into the vector. (So in the tests it should be from an `ldr d` after the existing `ldr q`. They currently use an ext from the vector).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141693/new/

https://reviews.llvm.org/D141693