[llvm] 5f1c6d4 - [AVR][NFC] Refactor 'AVRAsmPrinter::PrintAsmOperand'
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 30 19:24:48 PST 2023
Author: Ben Shi
Date: 2023-01-31T11:24:34+08:00
New Revision: 5f1c6d4444f770c3442a8f00ae813678e180b20a
URL: https://github.com/llvm/llvm-project/commit/5f1c6d4444f770c3442a8f00ae813678e180b20a
DIFF: https://github.com/llvm/llvm-project/commit/5f1c6d4444f770c3442a8f00ae813678e180b20a.diff
LOG: [AVR][NFC] Refactor 'AVRAsmPrinter::PrintAsmOperand'
Reviewed By: Chenbing.Zheng, aykevl
Differential Revision: https://reviews.llvm.org/D142170
Added:
Modified:
llvm/lib/Target/AVR/AVRAsmPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
index c0372e10ff9a3..0e6ec0268f857 100644
--- a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
+++ b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp
@@ -101,56 +101,51 @@ bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) {
// Default asm printer can only deal with some extra codes,
// so try it first.
- bool Error = AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
-
- if (Error && ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0)
- return true; // Unknown modifier.
+ if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
+ return false;
- if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
- const MachineOperand &RegOp = MI->getOperand(OpNum);
+ const MachineOperand &MO = MI->getOperand(OpNum);
- assert(RegOp.isReg() && "Operand must be a register when you're"
- "using 'A'..'Z' operand extracodes.");
- Register Reg = RegOp.getReg();
+ if (ExtraCode && ExtraCode[0]) {
+ // Unknown extra code.
+ if (ExtraCode[1] != 0 || ExtraCode[0] < 'A' || ExtraCode[0] > 'Z')
+ return true;
- unsigned ByteNumber = ExtraCode[0] - 'A';
+ // Operand must be a register when using 'A' ~ 'Z' extra code.
+ if (!MO.isReg())
+ return true;
- unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
- unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
- (void)NumOpRegs;
+ Register Reg = MO.getReg();
- const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
- const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+ unsigned ByteNumber = ExtraCode[0] - 'A';
+ unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
+ unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
- const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
- unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
- assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
+ const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- unsigned RegIdx = ByteNumber / BytesPerReg;
- if (RegIdx >= NumOpRegs)
- return true;
- Reg = MI->getOperand(OpNum + RegIdx).getReg();
+ const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
+ unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
+ assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
- if (BytesPerReg == 2) {
- Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
- : AVR::sub_lo);
- }
+ unsigned RegIdx = ByteNumber / BytesPerReg;
+ if (RegIdx >= NumOpRegs)
+ return true;
+ Reg = MI->getOperand(OpNum + RegIdx).getReg();
- O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
- return false;
+ if (BytesPerReg == 2) {
+ Reg = TRI.getSubReg(Reg,
+ ByteNumber % BytesPerReg ? AVR::sub_hi : AVR::sub_lo);
}
- }
- // Print global symbols.
- const auto &MO = MI->getOperand(OpNum);
- if (Error && MO.getType() == MachineOperand::MO_GlobalAddress) {
- PrintSymbolOperand(MO, O);
+ O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
return false;
}
- if (Error)
- printOperand(MI, OpNum, O);
+ if (MO.getType() == MachineOperand::MO_GlobalAddress)
+ PrintSymbolOperand(MO, O); // Print global symbols.
+ else
+ printOperand(MI, OpNum, O); // Fallback to ordinary cases.
return false;
}
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