[llvm] 7087f05 - [PowerPC] Pre-commit test for fix to peephole opt

Nemanja Ivanovic via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 30 19:01:45 PST 2023


Author: Nemanja Ivanovic
Date: 2023-01-30T21:01:21-06:00
New Revision: 7087f053f635f04beaa0da5e897d942be245688b

URL: https://github.com/llvm/llvm-project/commit/7087f053f635f04beaa0da5e897d942be245688b
DIFF: https://github.com/llvm/llvm-project/commit/7087f053f635f04beaa0da5e897d942be245688b.diff

LOG: [PowerPC] Pre-commit test for fix to peephole opt

This just adds a test case with current code gen. The patch
with the fix will correct the code gen.

Added: 
    llvm/test/CodeGen/PowerPC/no-misaligned-tocl.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/no-misaligned-tocl.ll b/llvm/test/CodeGen/PowerPC/no-misaligned-tocl.ll
new file mode 100644
index 0000000000000..f278411667daa
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/no-misaligned-tocl.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
+%0 = type <{ [7 x i8], i32, float, float, double, double, ppc_fp128 }>
+
+ at var = external dso_local unnamed_addr global %0, align 16
+ at ans = external dso_local unnamed_addr global i32, align 4
+
+define dso_local signext i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    addis r3, r2, var at toc@ha
+; CHECK-NEXT:    lis r4, 0
+; CHECK-NEXT:    lwa r3, var at toc@l+7(r3)
+; CHECK-NEXT:    ori r4, r4, 50000
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    addis r4, r2, ans at toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, ans at toc@l(r4)
+bb:
+  %i = load i32, ptr getelementptr inbounds (%0, ptr @var, i64 0, i32 1), align 4
+  %i1 = icmp slt i32 %i, 50000
+  %i2 = zext i1 %i1 to i32
+  store i32 %i2, ptr @ans, align 4
+  unreachable
+}


        


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