[PATCH] D108961: [RISCV] MC relaxation for out-of-range conditional branch.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:221
+
+  if (IsEqTest && SrcReg1.getReg() == RISCV::X0)
+    std::swap(SrcReg1, SrcReg2);
----------------
reames wrote:
> Doing this when we're not going to use the compressed instruction seems like an odd canonicalization from the assembler.  Not objecting, just wondering why.  
Probably because it made it easier to write the expression for UseComperssBr as a single condition. I'll rework it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108961/new/

https://reviews.llvm.org/D108961