[PATCH] D129927: [MachineScheduler] Try to issue the load instruction preferentially

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.
Herald added a subscriber: StephenFan.

I find it is **A57UnitL** Resource limited in the A57 backend.  
So, after I temporarily tried to adjust the A57UnitL number to 2, the load instruction would be issue first.
In fact, the current architecture is not VLIW, and only one instruction can be sent in a cycle, so will the A57UnitL really have a resource bottleneck in the pipeline?

- def A57UnitL : ProcResource<2>;  // Type L micro-ops

  ** ScheduleDAGMI::schedule picking next node
  Queue TopQ.P: 
  Queue TopQ.A: 0 1 5 
    TopQ.A RemainingLatency 0 + 0c > CritPath 17
    Cand SU(0) ORDER                              
  Pick Top TOP-PATH  
  Scheduling SU(0) renamable $q1, renamable $q2 = LDPQi renamable $x9, -1 :: (load (s128) from %ir.scevgep10, align 8), (load (s128) from %ir.lsr.iv79, align 8)
    Ready @0c
    A57UnitL +2x6u
    *** Critical resource A57UnitL: 2c
    TopQ.A BotLatency SU(0) 17c
    *** Max MOps 3 at cycle 0
  Cycle: 1 TopQ.A
  TopQ.A @1c
    Retired: 3
    Executed: 2c
    Critical: 2c, 2 A57UnitL
    ExpectedLatency: 0c
    - Resource limited.
  ** ScheduleDAGMI::schedule picking next node
  Queue TopQ.P: 
  Queue TopQ.A: 5 1 7 
    TopQ.A RemainingLatency 0 + 1c > CritPath 17
    TopQ.A ResourceLimited: A57UnitL
    Cand SU(5) ORDER                              
  Pick Top RES-REDUCE
  Scheduling SU(5) renamable $x2 = SUBSXri renamable $x2, 4, 0, implicit-def $nzcv
    Ready @1c
    A57UnitI +1x3u
  TopQ.A @1c
    Retired: 4
    Executed: 2c
    Critical: 2c, 2 A57UnitL
    ExpectedLatency: 0c
    - Resource limited.
  ** ScheduleDAGMI::schedule picking next node


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129927/new/

https://reviews.llvm.org/D129927