[PATCH] D142834: [RFC][X86][MC] Update and clarify the behavior of functions getX86SubSuperRegister*

[Kan Shengchen via Phabricator via llvm-commits]

skan added a comment.

In D142834#4089368 <https://reviews.llvm.org/D142834#4089368>, @pengfei wrote:

> In D142834#4088861 <https://reviews.llvm.org/D142834#4088861>, @skan wrote:
>
>> In D142834#4088826 <https://reviews.llvm.org/D142834#4088826>, @pengfei wrote:
>>
>>> In D142834#4088776 <https://reviews.llvm.org/D142834#4088776>, @skan wrote:
>>>
>>>> Not use report_fatal_error b/c it's unrelated to user input
>>>
>>> There will be difference with dedicated cases, e.g.: https://godbolt.org/z/oca6bj4s3
>>
>> It is an impossible case.  We can only access 8-bit high register for register a, b, c d in inline asm.
>>
>>   void f() {
>>     char x;
>>     asm volatile ("mov %h0, %h0" :"=r"(x)::);
>>     asm volatile ("mov %h0, %h0" :"=r"(x)::"%eax", "%ebx", "%ecx", "%edx", "edi", "esi");
>>   }
>>
>>
>>
>>   bash$ gcc -S 1.c -o -
>>           .file   "1.c"
>>           .text
>>           .globl  f
>>           .type   f, @function
>>   f:
>>   .LFB0:
>>           .cfi_startproc
>>           pushq   %rbp
>>           .cfi_def_cfa_offset 16
>>           .cfi_offset 6, -16
>>           movq    %rsp, %rbp
>>           .cfi_def_cfa_register 6
>>           pushq   %rbx
>>           .cfi_offset 3, -24
>>   #APP
>>   # 3 "1.c" 1
>>           mov %ah, %ah
>>   # 0 "" 2
>>   #NO_APP
>>           movb    %al, -9(%rbp)
>>   #APP
>>   # 4 "1.c" 1
>>   1.c: In function ‘f’:
>>   1.c:5:1: error: extended registers have no high halves
>
> I'm not sure if there's special requirment in LLVM. If we want to match with gcc, should we just need to replace `return getX86SubSuperRegisterOrZero(Reg, 64);` with `return X86::NoRegister`?

I think so. And it looks like one of `getX86SubSuperRegisterOrZero`  and `getX86SubSuperRegister` is redundant, let me do some clean work.


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https://reviews.llvm.org/D142834