[PATCH] D142797: [X86] Make `prefetchit{0/1}` emit an assembler warning if the operand is not rip-rel

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 493016.
goldstein.w.n added a comment.

Fix commit msg


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142797/new/

https://reviews.llvm.org/D142797

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/test/MC/X86/prefetchit-non-rip-op.s


Index: llvm/test/MC/X86/prefetchit-non-rip-op.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/prefetchit-non-rip-op.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown %s > %t 2> %t.err
+// RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 (%rdi)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 (%rcx)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 0x1(%rdx)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 0x12(%rsi)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 0x123(%r8, %rax)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 0x1234(%r9, %r10)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 (%r11, %r12)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 (%r13, %r14)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 0xabc(%rsp, %r15, 4)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 0xffffffff(%rbp, %rdi, 8)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 (%rsp, %rsi, 2)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 (%rdi, %r15, 4)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 0x80(, %r14, 8)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 0x3(, %r8, 4)
+
+// CHECK-STDERR: warning: 'prefetchit0' only supports RIP-relative address
+          prefetchit0 (, %rax, 2)
+
+// CHECK-STDERR: warning: 'prefetchit1' only supports RIP-relative address
+          prefetchit1 (, %rcx, 8)
Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -515,6 +515,16 @@
 /// Insert BoundaryAlignFragment before instructions to align branches.
 void X86AsmBackend::emitInstructionBegin(MCObjectStreamer &OS,
                                          const MCInst &Inst, const MCSubtargetInfo &STI) {
+  if ((Inst.getOpcode() == X86::PREFETCHIT0 ||
+       Inst.getOpcode() == X86::PREFETCHIT1) &&
+      !isRIPRelative(Inst, *MCII)) {
+    OS.getAssembler().getContext().reportWarning(
+        Inst.getLoc(),
+        Twine((Inst.getOpcode() == X86::PREFETCHIT0 ? "'prefetchit0'"
+                                                    : "'prefetchit1'")) +
+            " only supports RIP-relative address");
+  }
+
   CanPadInst = canPadInst(Inst, OS);
 
   if (!canPadBranches(OS))


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D142797.493016.patch
Type: text/x-patch
Size: 3146 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230128/9f5cb1ce/attachment.bin>