[llvm] e078201 - [Target] Use llvm::count{l,r}_{zero,one} (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 28 09:23:16 PST 2023
Author: Kazu Hirata
Date: 2023-01-28T09:23:07-08:00
New Revision: e0782018352fc4d7e104e82edf380d895d4abdd5
URL: https://github.com/llvm/llvm-project/commit/e0782018352fc4d7e104e82edf380d895d4abdd5
DIFF: https://github.com/llvm/llvm-project/commit/e0782018352fc4d7e104e82edf380d895d4abdd5.diff
LOG: [Target] Use llvm::count{l,r}_{zero,one} (NFC)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIModeRegister.cpp
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/lib/Target/ARM/ARMBasicBlockInfo.h
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/VE/VE.h
llvm/lib/Target/X86/X86FloatingPoint.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
index 4f324198f3dc..6b6fd6562642 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
@@ -268,8 +268,8 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
unsigned LastShift = 0; // LSL amount for last MOVK
if (Imm != 0) {
- unsigned LZ = countLeadingZeros(Imm);
- unsigned TZ = countTrailingZeros(Imm);
+ unsigned LZ = llvm::countl_zero(Imm);
+ unsigned TZ = llvm::countr_zero(Imm);
Shift = (TZ / 16) * 16;
LastShift = ((63 - LZ) / 16) * 16;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 3ebcc24beab8..74f9c4c48d7d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2306,8 +2306,9 @@ static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
}
LSB = SrlImm;
- MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
- : countTrailingOnes<uint64_t>(AndImm)) -
+ MSB = SrlImm +
+ (VT == MVT::i32 ? llvm::countr_one<uint32_t>(AndImm)
+ : llvm::countr_one<uint64_t>(AndImm)) -
1;
if (ClampMSB)
// Since we're moving the extend before the right shift operation, we need
@@ -2949,8 +2950,8 @@ static bool isBitfieldPositioningOpFromAnd(SelectionDAG *CurDAG, SDValue Op,
if (!BiggerPattern && !AndOp0.hasOneUse())
return false;
- DstLSB = countTrailingZeros(NonZeroBits);
- Width = countTrailingOnes(NonZeroBits >> DstLSB);
+ DstLSB = llvm::countr_zero(NonZeroBits);
+ Width = llvm::countr_one(NonZeroBits >> DstLSB);
// Bail out on large Width. This happens when no proper combining / constant
// folding was performed.
@@ -3008,7 +3009,7 @@ static bool isSeveralBitsPositioningOpFromShl(const uint64_t ShlImm, SDValue Op,
// For example, xyz11111 (with {x,y,z} being 0 or 1) is fine if ShlImm >= 3;
// the AND result corresponding to those bits are shifted out, so it's fine
// to not extract them.
- Width = countTrailingOnes(ShiftedAndImm);
+ Width = llvm::countr_one(ShiftedAndImm);
DstLSB = ShlImm;
Src = Op0.getOperand(0);
return true;
@@ -3038,8 +3039,8 @@ static bool isBitfieldPositioningOpFromShl(SelectionDAG *CurDAG, SDValue Op,
if (isSeveralBitsPositioningOpFromShl(ShlImm, Op, Src, DstLSB, Width))
return true;
- DstLSB = countTrailingZeros(NonZeroBits);
- Width = countTrailingOnes(NonZeroBits >> DstLSB);
+ DstLSB = llvm::countr_zero(NonZeroBits);
+ Width = llvm::countr_one(NonZeroBits >> DstLSB);
if (ShlImm != uint64_t(DstLSB) && !BiggerPattern)
return false;
@@ -3103,7 +3104,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
}
// BFI/BFXIL dst, src, #lsb, #width.
- int LSB = countTrailingOnes(NotKnownZero);
+ int LSB = llvm::countr_one(NotKnownZero);
int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
// BFI/BFXIL is an alias of BFM, so translate to BFM operands.
@@ -3181,10 +3182,10 @@ static bool isWorthFoldingIntoOrrWithShift(SDValue Dst, SelectionDAG *CurDAG,
// the dependency chain is improved after the transformation.
uint64_t SrlImm;
if (isOpcWithIntImmediate(DstOp0.getNode(), ISD::SRL, SrlImm)) {
- uint64_t NumTrailingZeroInShiftedMask = countTrailingZeros(AndImm);
+ uint64_t NumTrailingZeroInShiftedMask = llvm::countr_zero(AndImm);
if ((SrlImm + NumTrailingZeroInShiftedMask) < SizeInBits) {
unsigned MaskWidth =
- countTrailingOnes(AndImm >> NumTrailingZeroInShiftedMask);
+ llvm::countr_one(AndImm >> NumTrailingZeroInShiftedMask);
unsigned UBFMOpc =
(VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
SDNode *UBFMNode = CurDAG->getMachineNode(
@@ -3459,7 +3460,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
SDValue Src = And1->getOperand(0);
SDValue Dst = And0->getOperand(0);
- unsigned LSB = countTrailingZeros(Mask1Imm);
+ unsigned LSB = llvm::countr_zero(Mask1Imm);
int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
// The BFXIL inserts the low-order bits from a source register, so right
@@ -3647,7 +3648,7 @@ bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) {
!isOpcWithIntImmediate(ShiftAmt.getNode(), AArch64ISD::ANDS, MaskImm))
return false;
- if (countTrailingOnes(MaskImm) < Bits)
+ if ((unsigned)llvm::countr_one(MaskImm) < Bits)
return false;
NewShiftAmt = ShiftAmt->getOperand(0);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ff4f36873604..fd5962c0951a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13728,7 +13728,7 @@ bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
// Get the shift amount based on the scaling factor:
// log2(sizeof(IdxTy)) - log2(8).
uint64_t ShiftAmt =
- countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy).getFixedValue()) -
+ llvm::countr_zero(DL.getTypeStoreSizeInBits(IdxTy).getFixedValue()) -
3;
// Is the constant foldable in the shift of the addressing mode?
// I.e., shift amount is between 1 and 4 inclusive.
@@ -15040,7 +15040,7 @@ bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
if (BitSize == 32)
Val &= (1LL << 32) - 1;
- unsigned LZ = countLeadingZeros((uint64_t)Val);
+ unsigned LZ = llvm::countl_zero((uint64_t)Val);
unsigned Shift = (63 - LZ) / 16;
// MOVZ is free so return true for one or fewer MOVK.
return Shift < 3;
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 0f9d45e86b21..4c495c203a80 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -136,7 +136,7 @@ static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) {
// consecutive ones. We can split it in to two bitmask immediate like
// 0b00000000001111111111110000000000 and 0b11111111111000000000011111111111.
// If we do AND with these two bitmask immediate, we can see original one.
- unsigned LowestBitSet = countTrailingZeros(UImm);
+ unsigned LowestBitSet = llvm::countr_zero(UImm);
unsigned HighestBitSet = Log2_64(UImm);
// Create a mask which is filled with one from the position of lowest bit set
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f42ddf7e53ea..b3f832618d6e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4939,7 +4939,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
if (isa<MCConstantExpr>(SubExprVal)) {
uint64_t Imm = (cast<MCConstantExpr>(SubExprVal))->getValue();
uint32_t ShiftAmt = 0, MaxShiftAmt = IsXReg ? 48 : 16;
- while(Imm > 0xFFFF && countTrailingZeros(Imm) >= 16) {
+ while (Imm > 0xFFFF && llvm::countr_zero(Imm) >= 16) {
ShiftAmt += 16;
Imm >>= 16;
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
index 71862e85b49c..33c08bfc6de6 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
@@ -237,17 +237,17 @@ static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
Imm &= Mask;
if (isShiftedMask_64(Imm)) {
- I = countTrailingZeros(Imm);
+ I = llvm::countr_zero(Imm);
assert(I < 64 && "undefined behavior");
- CTO = countTrailingOnes(Imm >> I);
+ CTO = llvm::countr_one(Imm >> I);
} else {
Imm |= ~Mask;
if (!isShiftedMask_64(~Imm))
return false;
- unsigned CLO = countLeadingOnes(Imm);
+ unsigned CLO = llvm::countl_one(Imm);
I = 64 - CLO;
- CTO = CLO + countTrailingOnes(Imm) - (64 - Size);
+ CTO = CLO + llvm::countr_one(Imm) - (64 - Size);
}
// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
@@ -298,7 +298,7 @@ static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
unsigned imms = val & 0x3f;
assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
- int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+ int len = 31 - llvm::countl_zero((N << 6) | (~imms & 0x3f));
assert(len >= 0 && "undefined logical immediate encoding");
unsigned size = (1 << len);
unsigned R = immr & (size - 1);
@@ -327,7 +327,7 @@ static inline bool isValidDecodeLogicalImmediate(uint64_t val,
if (regSize == 32 && N != 0) // undefined logical immediate encoding
return false;
- int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+ int len = 31 - llvm::countl_zero((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
return false;
unsigned size = (1 << len);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index da819b6d4a23..0f6682e80c42 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -701,7 +701,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
if ((PsInputBits & 0x7F) == 0 ||
((PsInputBits & 0xF) == 0 &&
(PsInputBits >> 11 & 1)))
- Info->markPSInputEnabled(countTrailingZeros(Info->getPSInputAddr()));
+ Info->markPSInputEnabled(llvm::countr_zero(Info->getPSInputAddr()));
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f4d49fcc0838..7dda63d2ce41 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4365,7 +4365,7 @@ SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
return V;
unsigned Mask = Arg.getMask();
- unsigned Shift = countTrailingZeros<unsigned>(Mask);
+ unsigned Shift = llvm::countr_zero<unsigned>(Mask);
V = DAG.getNode(ISD::SRL, SL, VT, V,
DAG.getShiftAmountConstant(Shift, VT, SL));
return DAG.getNode(ISD::AND, SL, VT, V,
@@ -4747,7 +4747,7 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
case Intrinsic::amdgcn_workitem_id_z: {
unsigned MaxValue = Subtarget->getMaxWorkitemID(
DAG.getMachineFunction().getFunction(), workitemIntrinsicDim(IID));
- Known.Zero.setHighBits(countLeadingZeros(MaxValue));
+ Known.Zero.setHighBits(llvm::countl_zero(MaxValue));
break;
}
default:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 20fca4638118..ba0a4ff86fcf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3259,7 +3259,7 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
// TODO: Should we try to emit this once in the entry block?
const LLT S32 = LLT::scalar(32);
const unsigned Mask = Arg->getMask();
- const unsigned Shift = countTrailingZeros<unsigned>(Mask);
+ const unsigned Shift = llvm::countr_zero<unsigned>(Mask);
Register AndMaskSrc = LiveIn;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 796a5077325c..2b1646af175f 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -284,7 +284,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// Return the number of high bits known to be zero for a frame index.
unsigned getKnownHighZeroBitsForFrameIndex() const {
- return countLeadingZeros(getMaxWaveScratchSize()) + getWavefrontSizeLog2();
+ return llvm::countl_zero(getMaxWaveScratchSize()) + getWavefrontSizeLog2();
}
int getLDSBankCount() const {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 056daee92b27..514699128412 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2453,7 +2453,7 @@ SDValue SITargetLowering::LowerFormalArguments(
unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
if ((PsInputBits & 0x7F) == 0 ||
((PsInputBits & 0xF) == 0 && (PsInputBits >> 11 & 1)))
- Info->markPSInputEnabled(countTrailingZeros(Info->getPSInputAddr()));
+ Info->markPSInputEnabled(llvm::countr_zero(Info->getPSInputAddr()));
}
} else if (IsKernel) {
assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
@@ -11786,7 +11786,7 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// Set which texture component corresponds to the lane.
unsigned Comp;
for (unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
- Comp = countTrailingZeros(Dmask);
+ Comp = llvm::countr_zero(Dmask);
Dmask &= ~(1 << Comp);
}
@@ -12613,7 +12613,7 @@ static void knownBitsForWorkitemID(const GCNSubtarget &ST, GISelKnownBits &KB,
KnownBits &Known, unsigned Dim) {
unsigned MaxValue =
ST.getMaxWorkitemID(KB.getMachineFunction().getFunction(), Dim);
- Known.Zero.setHighBits(countLeadingZeros(MaxValue));
+ Known.Zero.setHighBits(llvm::countl_zero(MaxValue));
}
void SITargetLowering::computeKnownBitsForTargetInstr(
@@ -12644,7 +12644,7 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
// based on the actual size because we don't know if it's accurate or not
// at any given point.
Known.Zero.setHighBits(
- countLeadingZeros(getSubtarget()->getAddressableLocalMemorySize()));
+ llvm::countl_zero(getSubtarget()->getAddressableLocalMemorySize()));
break;
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2cbc90219334..e508d206f6c5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8622,7 +8622,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
else
return false;
- unsigned BitNo = countTrailingZeros((uint64_t)Mask);
+ unsigned BitNo = llvm::countr_zero((uint64_t)Mask);
if (IsSigned && BitNo == SrcSize - 1)
return false;
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 2b5ca33b0e4f..962f3383146c 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -887,7 +887,7 @@ bool SILoadStoreOptimizer::dmasksCanBeCombined(const CombineInfo &CI,
unsigned MaxMask = std::max(CI.DMask, Paired.DMask);
unsigned MinMask = std::min(CI.DMask, Paired.DMask);
- unsigned AllowedBitsForMin = llvm::countTrailingZeros(MaxMask);
+ unsigned AllowedBitsForMin = llvm::countr_zero(MaxMask);
if ((1u << AllowedBitsForMin) <= MinMask)
return false;
@@ -926,7 +926,7 @@ static unsigned getBufferFormatWithCompCount(unsigned OldFormat,
// - if Lo == 0, return 0 (even though the "- 1" below underflows
// - if Lo > Hi, return 0 (as if the range wrapped around)
static uint32_t mostAlignedValueInRange(uint32_t Lo, uint32_t Hi) {
- return Hi & maskLeadingOnes<uint32_t>(countLeadingZeros((Lo - 1) ^ Hi) + 1);
+ return Hi & maskLeadingOnes<uint32_t>(llvm::countl_zero((Lo - 1) ^ Hi) + 1);
}
bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI,
diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
index 0d48c3159c6f..f0b925d1d5cb 100644
--- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
+++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
@@ -222,8 +222,8 @@ Status SIModeRegister::getInstructionMode(MachineInstr &MI,
void SIModeRegister::insertSetreg(MachineBasicBlock &MBB, MachineInstr *MI,
const SIInstrInfo *TII, Status InstrMode) {
while (InstrMode.Mask) {
- unsigned Offset = countTrailingZeros<unsigned>(InstrMode.Mask);
- unsigned Width = countTrailingOnes<unsigned>(InstrMode.Mask >> Offset);
+ unsigned Offset = llvm::countr_zero<unsigned>(InstrMode.Mask);
+ unsigned Width = llvm::countr_one<unsigned>(InstrMode.Mask >> Offset);
unsigned Value = (InstrMode.Mode >> Offset) & ((1 << Width) - 1);
BuildMI(MBB, MI, nullptr, TII->get(AMDGPU::S_SETREG_IMM32_B32))
.addImm(Value)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index bec07d990380..ad650023b04d 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -497,7 +497,7 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
if (Opc == AMDGPU::S_AND_B32) {
if (isPowerOf2_32(~Imm)) {
- NewImm = countTrailingOnes(Imm);
+ NewImm = llvm::countr_one(Imm);
Opc = AMDGPU::S_BITSET0_B32;
} else if (AMDGPU::isInlinableLiteral32(~Imm, ST->hasInv2PiInlineImm())) {
NewImm = ~Imm;
@@ -505,7 +505,7 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
}
} else if (Opc == AMDGPU::S_OR_B32) {
if (isPowerOf2_32(Imm)) {
- NewImm = countTrailingZeros(Imm);
+ NewImm = llvm::countr_zero(Imm);
Opc = AMDGPU::S_BITSET1_B32;
} else if (AMDGPU::isInlinableLiteral32(~Imm, ST->hasInv2PiInlineImm())) {
NewImm = ~Imm;
diff --git a/llvm/lib/Target/ARM/ARMBasicBlockInfo.h b/llvm/lib/Target/ARM/ARMBasicBlockInfo.h
index 47d9a4049fa0..daf8f9b4b836 100644
--- a/llvm/lib/Target/ARM/ARMBasicBlockInfo.h
+++ b/llvm/lib/Target/ARM/ARMBasicBlockInfo.h
@@ -80,7 +80,7 @@ struct BasicBlockInfo {
// If the block size isn't a multiple of the known bits, assume the
// worst case padding.
if (Size & ((1u << Bits) - 1))
- Bits = countTrailingZeros(Size);
+ Bits = llvm::countr_zero(Size);
return Bits;
}
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index e880e9d66fc1..a271dedb0162 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -443,7 +443,7 @@ void ARMDAGToDAGISel::PreprocessISelDAG() {
continue;
// Check if the AND mask is an immediate of the form: 000.....1111111100
- unsigned TZ = countTrailingZeros(And_imm);
+ unsigned TZ = llvm::countr_zero(And_imm);
if (TZ != 1 && TZ != 2)
// Be conservative here. Shifter operands aren't always free. e.g. On
// Swift, left shifter operand of 1 / 2 for free but others are not.
@@ -3365,7 +3365,7 @@ bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
And_imm &= -1U >> Srl_imm;
// Note: The width operand is encoded as width-1.
- unsigned Width = countTrailingOnes(And_imm) - 1;
+ unsigned Width = llvm::countr_one(And_imm) - 1;
unsigned LSB = Srl_imm;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
@@ -3431,11 +3431,11 @@ bool ARMDAGToDAGISel::tryV6T2BitfieldExtractOp(SDNode *N, bool isSigned) {
if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
isShiftedMask_32(And_imm)) {
unsigned Srl_imm = 0;
- unsigned LSB = countTrailingZeros(And_imm);
+ unsigned LSB = llvm::countr_zero(And_imm);
// Shift must be the same as the ands lsb
if (isInt32Immediate(N->getOperand(1), Srl_imm) && Srl_imm == LSB) {
assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
- unsigned MSB = 31 - countLeadingZeros(And_imm);
+ unsigned MSB = 31 - llvm::countl_zero(And_imm);
// Note: The width operand is encoded as width-1.
unsigned Width = MSB - LSB;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2e78b52d0993..8a28e6b4e4fd 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4788,7 +4788,7 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
uint64_t RHSV = RHSC->getZExtValue();
if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
- unsigned ShiftBits = countLeadingZeros(Mask);
+ unsigned ShiftBits = llvm::countl_zero(Mask);
if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
@@ -5335,10 +5335,10 @@ static SDValue LowerSaturatingConditional(SDValue Op, SelectionDAG &DAG) {
SDLoc dl(Op);
if (Val1 == ~Val2)
return DAG.getNode(ARMISD::SSAT, dl, VT, V2Tmp,
- DAG.getConstant(countTrailingOnes(K), dl, VT));
+ DAG.getConstant(llvm::countr_one(K), dl, VT));
if (NegVal == 0)
return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp,
- DAG.getConstant(countTrailingOnes(K), dl, VT));
+ DAG.getConstant(llvm::countr_one(K), dl, VT));
return SDValue();
}
@@ -14079,7 +14079,7 @@ static SDValue PerformMULCombine(SDNode *N,
return SDValue();
int64_t MulAmt = C->getSExtValue();
- unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
+ unsigned ShiftAmt = llvm::countr_zero<uint64_t>(MulAmt);
ShiftAmt = ShiftAmt & (32 - 1);
SDValue V = N->getOperand(0);
@@ -14192,7 +14192,7 @@ static SDValue CombineANDShift(SDNode *N,
// First pattern: right shift, then mask off leading bits.
// FIXME: Use demanded bits?
if (!LeftShift && isMask_32(C1)) {
- uint32_t C3 = countLeadingZeros(C1);
+ uint32_t C3 = llvm::countl_zero(C1);
if (C2 < C3) {
SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
DAG.getConstant(C3 - C2, DL, MVT::i32));
@@ -14203,7 +14203,7 @@ static SDValue CombineANDShift(SDNode *N,
// First pattern, reversed: left shift, then mask off trailing bits.
if (LeftShift && isMask_32(~C1)) {
- uint32_t C3 = countTrailingZeros(C1);
+ uint32_t C3 = llvm::countr_zero(C1);
if (C2 < C3) {
SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
DAG.getConstant(C3 - C2, DL, MVT::i32));
@@ -14215,8 +14215,8 @@ static SDValue CombineANDShift(SDNode *N,
// Second pattern: left shift, then mask off leading bits.
// FIXME: Use demanded bits?
if (LeftShift && isShiftedMask_32(C1)) {
- uint32_t Trailing = countTrailingZeros(C1);
- uint32_t C3 = countLeadingZeros(C1);
+ uint32_t Trailing = llvm::countr_zero(C1);
+ uint32_t C3 = llvm::countl_zero(C1);
if (Trailing == C2 && C2 + C3 < 32) {
SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
DAG.getConstant(C2 + C3, DL, MVT::i32));
@@ -14228,8 +14228,8 @@ static SDValue CombineANDShift(SDNode *N,
// Second pattern, reversed: right shift, then mask off trailing bits.
// FIXME: Handle other patterns of known/demanded bits.
if (!LeftShift && isShiftedMask_32(C1)) {
- uint32_t Leading = countLeadingZeros(C1);
- uint32_t C3 = countTrailingZeros(C1);
+ uint32_t Leading = llvm::countl_zero(C1);
+ uint32_t C3 = llvm::countr_zero(C1);
if (Leading == C2 && C2 + C3 < 32) {
SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0),
DAG.getConstant(C2 + C3, DL, MVT::i32));
@@ -14400,7 +14400,7 @@ static SDValue PerformORCombineToBFI(SDNode *N,
return SDValue();
if (ARM::isBitFieldInvertedMask(Mask)) {
- Val >>= countTrailingZeros(~Mask);
+ Val >>= llvm::countr_zero(~Mask);
Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
DAG.getConstant(Val, DL, MVT::i32),
@@ -14428,7 +14428,7 @@ static SDValue PerformORCombineToBFI(SDNode *N,
(Mask == 0xffff || Mask == 0xffff0000))
return SDValue();
// 2a
- unsigned amt = countTrailingZeros(Mask2);
+ unsigned amt = llvm::countr_zero(Mask2);
Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
DAG.getConstant(amt, DL, MVT::i32));
Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
@@ -14445,7 +14445,7 @@ static SDValue PerformORCombineToBFI(SDNode *N,
(Mask2 == 0xffff || Mask2 == 0xffff0000))
return SDValue();
// 2b
- unsigned lsb = countTrailingZeros(Mask);
+ unsigned lsb = llvm::countr_zero(Mask);
Res = DAG.getNode(ISD::SRL, DL, VT, N00,
DAG.getConstant(lsb, DL, MVT::i32));
Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
@@ -14464,7 +14464,7 @@ static SDValue PerformORCombineToBFI(SDNode *N,
// where lsb(mask) == #shamt and masked bits of B are known zero.
SDValue ShAmt = N00.getOperand(1);
unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
- unsigned LSB = countTrailingZeros(Mask);
+ unsigned LSB = llvm::countr_zero(Mask);
if (ShAmtC != LSB)
return SDValue();
@@ -14753,7 +14753,7 @@ static SDValue PerformBFICombine(SDNode *N, SelectionDAG &DAG) {
if (!N11C)
return SDValue();
unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
- unsigned LSB = countTrailingZeros(~InvMask);
+ unsigned LSB = llvm::countr_zero(~InvMask);
unsigned Width = llvm::bit_width<unsigned>(~InvMask) - LSB;
assert(Width <
static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
@@ -17511,7 +17511,7 @@ static SDValue PerformShiftCombine(SDNode *N,
if (AndMask == 255 || AndMask == 65535)
return SDValue();
if (isMask_32(AndMask)) {
- uint32_t MaskedBits = countLeadingZeros(AndMask);
+ uint32_t MaskedBits = llvm::countl_zero(AndMask);
if (MaskedBits > ShiftAmt) {
SDLoc DL(N);
SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0),
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 207cf32590cb..7d4fc9760d69 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -318,7 +318,7 @@ class ARMAsmParser : public MCTargetAsmParser {
bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
bool lastInITBlock() {
- return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
+ return ITState.CurPosition == 4 - (unsigned)llvm::countr_zero(ITState.Mask);
}
void forwardITPosition() {
@@ -326,7 +326,7 @@ class ARMAsmParser : public MCTargetAsmParser {
// Move to the next instruction in the IT block, if there is one. If not,
// mark the block as done, except for implicit IT blocks, which we leave
// open until we find an instruction that can't be added to it.
- unsigned TZ = countTrailingZeros(ITState.Mask);
+ unsigned TZ = llvm::countr_zero(ITState.Mask);
if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
ITState.CurPosition = ~0U; // Done with the IT block after this.
}
@@ -336,7 +336,7 @@ class ARMAsmParser : public MCTargetAsmParser {
assert(inImplicitITBlock());
assert(ITState.CurPosition > 1);
ITState.CurPosition--;
- unsigned TZ = countTrailingZeros(ITState.Mask);
+ unsigned TZ = llvm::countr_zero(ITState.Mask);
unsigned NewMask = 0;
NewMask |= ITState.Mask & (0xC << TZ);
NewMask |= 0x2 << TZ;
@@ -384,7 +384,7 @@ class ARMAsmParser : public MCTargetAsmParser {
assert(!isITBlockFull());
assert(Cond == ITState.Cond ||
Cond == ARMCC::getOppositeCondition(ITState.Cond));
- unsigned TZ = countTrailingZeros(ITState.Mask);
+ unsigned TZ = llvm::countr_zero(ITState.Mask);
unsigned NewMask = 0;
// Keep any existing condition bits.
NewMask |= ITState.Mask & (0xE << TZ);
@@ -423,7 +423,7 @@ class ARMAsmParser : public MCTargetAsmParser {
bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
void forwardVPTPosition() {
if (!inVPTBlock()) return;
- unsigned TZ = countTrailingZeros(VPTState.Mask);
+ unsigned TZ = llvm::countr_zero(VPTState.Mask);
if (++VPTState.CurPosition == 5 - TZ)
VPTState.CurPosition = ~0U;
}
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index fa696d8952e4..597eba23b601 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -71,7 +71,7 @@ namespace {
// is in the MCOperand format in which 1 means 'else' and 0 'then'.
void setITState(char Firstcond, char Mask) {
// (3 - the number of trailing zeros) is the number of then / else.
- unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
+ unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
assert(NumTZ <= 3 && "Invalid IT mask!");
// push condition codes onto the stack the correct order for the pops
@@ -110,7 +110,7 @@ namespace {
void setVPTState(char Mask) {
// (3 - the number of trailing zeros) is the number of then / else.
- unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
+ unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);
assert(NumTZ <= 3 && "Invalid VPT mask!");
// push predicates onto the stack the correct order for the pops
for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
index 8459b4ff2a14..3170d2a1284f 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
@@ -132,7 +132,7 @@ namespace ARM_AM {
if ((Imm & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
- unsigned TZ = countTrailingZeros(Imm);
+ unsigned TZ = llvm::countr_zero(Imm);
// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
// not 9.
@@ -145,7 +145,7 @@ namespace ARM_AM {
// For values like 0xF000000F, we should ignore the low 6 bits, then
// retry the hunt.
if (Imm & 63U) {
- unsigned TZ2 = countTrailingZeros(Imm & ~63U);
+ unsigned TZ2 = llvm::countr_zero(Imm & ~63U);
unsigned RotAmt2 = TZ2 & ~1;
if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
return (32-RotAmt2)&31; // HW rotates right, not left.
@@ -227,7 +227,7 @@ namespace ARM_AM {
if ((Imm & ~255U) == 0) return 0;
// Use CTZ to compute the shift amount.
- return countTrailingZeros(Imm);
+ return llvm::countr_zero(Imm);
}
/// isThumbImmShiftedVal - Return true if the specified value can be obtained
@@ -246,7 +246,7 @@ namespace ARM_AM {
if ((Imm & ~65535U) == 0) return 0;
// Use CTZ to compute the shift amount.
- return countTrailingZeros(Imm);
+ return llvm::countr_zero(Imm);
}
/// isThumbImm16ShiftedVal - Return true if the specified value can be
@@ -302,7 +302,7 @@ namespace ARM_AM {
/// encoding is possible.
/// See ARM Reference Manual A6.3.2.
inline int getT2SOImmValRotateVal(unsigned V) {
- unsigned RotAmt = countLeadingZeros(V);
+ unsigned RotAmt = llvm::countl_zero(V);
if (RotAmt >= 24)
return -1;
@@ -334,7 +334,7 @@ namespace ARM_AM {
inline unsigned getT2SOImmValRotate(unsigned V) {
if ((V & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
- unsigned RotAmt = countTrailingZeros(V);
+ unsigned RotAmt = llvm::countr_zero(V);
return (32 - RotAmt) & 31;
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 9f275145adfd..1ada656d72ef 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -739,7 +739,7 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
uint32_t v = ~MO.getImm();
- int32_t lsb = countTrailingZeros(v);
+ int32_t lsb = llvm::countr_zero(v);
int32_t width = llvm::bit_width(v) - lsb;
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
@@ -1073,7 +1073,7 @@ void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
// (3 - the number of trailing zeros) is the number of then / else.
unsigned Mask = MI->getOperand(OpNum).getImm();
- unsigned NumTZ = countTrailingZeros(Mask);
+ unsigned NumTZ = llvm::countr_zero(Mask);
assert(NumTZ <= 3 && "Invalid IT mask!");
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
if ((Mask >> Pos) & 1)
@@ -1657,7 +1657,7 @@ void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
// (3 - the number of trailing zeroes) is the number of them / else.
unsigned Mask = MI->getOperand(OpNum).getImm();
- unsigned NumTZ = countTrailingZeros(Mask);
+ unsigned NumTZ = llvm::countr_zero(Mask);
assert(NumTZ <= 3 && "Invalid VPT mask!");
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
bool T = ((Mask >> Pos) & 1) == 0;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index bafc0f853756..01a4498991d8 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1700,8 +1700,8 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
// msb of the mask.
const MCOperand &MO = MI.getOperand(Op);
uint32_t v = ~MO.getImm();
- uint32_t lsb = countTrailingZeros(v);
- uint32_t msb = (32 - countLeadingZeros (v)) - 1;
+ uint32_t lsb = llvm::countr_zero(v);
+ uint32_t msb = (32 - llvm::countl_zero(v)) - 1;
assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
return lsb | (msb << 5);
}
@@ -1988,7 +1988,7 @@ getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Unexpected operand type!");
- return countTrailingZeros((uint64_t)MO.getImm());
+ return llvm::countr_zero((uint64_t)MO.getImm());
}
template <unsigned start>
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
index 4686bb0b4509..62404f7add48 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
@@ -77,7 +77,7 @@ void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
// Compute the consecutive registers from r4 to r11.
uint32_t Mask = RegSave & 0xff0u;
- uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4.
+ uint32_t Range = llvm::countr_one(Mask >> 5); // Exclude r4.
// Mask off non-consecutive registers. Keep r4.
Mask &= ~(0xffffffe0u << Range);
@@ -111,7 +111,7 @@ void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
while (Regs) {
// Now look for a run of set bits. Remember the MSB and LSB of the run.
auto RangeMSB = llvm::bit_width(Regs);
- auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
+ auto RangeLen = llvm::countl_one(Regs << (32 - RangeMSB));
auto RangeLSB = RangeMSB - RangeLen;
int Opcode = RangeLSB >= 16
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 1b24c289061d..1a5370e79865 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -398,7 +398,7 @@ void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
} else {
// Use one T2 instruction to reduce NumBytes
// FIXME: Move this to ARMAddressingModes.h?
- unsigned RotAmt = countLeadingZeros(ThisVal);
+ unsigned RotAmt = llvm::countl_zero(ThisVal);
ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
NumBytes &= ~ThisVal;
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
@@ -603,7 +603,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
// Otherwise, extract 8 adjacent bits from the immediate into this
// t2ADDri/t2SUBri.
- unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
+ unsigned RotAmt = llvm::countl_zero<unsigned>(Offset);
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
// We will handle these bits from offset, clear them.
diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
index 3356d56481e5..43c2c89d259e 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
@@ -19,8 +19,7 @@ ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask,
ARMVCC::VPTCodes Kind) {
using PredBlockMask = ARM::PredBlockMask;
assert(Kind != ARMVCC::None && "Cannot expand a mask with None!");
- assert(countTrailingZeros((unsigned)BlockMask) != 0 &&
- "Mask is already full");
+ assert(llvm::countr_zero((unsigned)BlockMask) != 0 && "Mask is already full");
auto ChooseMask = [&](PredBlockMask AddedThen, PredBlockMask AddedElse) {
return Kind == ARMVCC::Then ? AddedThen : AddedElse;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index aab543dde76b..a027f2cedca0 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -329,7 +329,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI,
int FI = op(1).getIndex();
int Off = op(2).getImm();
unsigned A = MFI.getObjectAlign(FI).value() + std::abs(Off);
- unsigned L = countTrailingZeros(A);
+ unsigned L = llvm::countr_zero(A);
RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
RC.fill(0, L, BT::BitValue::Zero);
return rr0(RC, Outputs);
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index 56fb50cdb09e..400bb6cfc731 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -1745,7 +1745,7 @@ bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
// "alignment" as Diff.
uint32_t UD = Diff;
OffsetRange R = getOffsetRange(MI.getOperand(0));
- uint32_t A = std::min<uint32_t>(R.Align, 1u << countTrailingZeros(UD));
+ uint32_t A = std::min<uint32_t>(R.Align, 1u << llvm::countr_zero(UD));
D &= ~(A-1);
}
BuildMI(MBB, At, dl, HII->get(IdxOpc))
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 855c4ac4bca2..d6c459f4f1cb 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1170,9 +1170,9 @@ void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) {
continue;
uint32_t Mask = MN->getZExtValue();
// Examine the mask.
- uint32_t TZ = countTrailingZeros(Mask);
- uint32_t M1 = countTrailingOnes(Mask >> TZ);
- uint32_t LZ = countLeadingZeros(Mask);
+ uint32_t TZ = llvm::countr_zero(Mask);
+ uint32_t M1 = llvm::countr_one(Mask >> TZ);
+ uint32_t LZ = llvm::countl_zero(Mask);
// Trailing zeros + middle ones + leading zeros must equal the width.
if (TZ + M1 + LZ != 32)
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 202fc473f9e4..ec3e052b600b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1940,7 +1940,7 @@ HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign,
return true;
unsigned Addr = CA->getZExtValue();
Align HaveAlign =
- Addr != 0 ? Align(1ull << countTrailingZeros(Addr)) : NeedAlign;
+ Addr != 0 ? Align(1ull << llvm::countr_zero(Addr)) : NeedAlign;
if (HaveAlign >= NeedAlign)
return true;
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 5774cad0f102..d60969f04725 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -101,7 +101,7 @@ unsigned HexagonResource::setWeight(unsigned s) {
return Weight = 0;
unsigned Ctpop = llvm::popcount(Units);
- unsigned Cttz = countTrailingZeros(Units);
+ unsigned Cttz = llvm::countr_zero(Units);
Weight = (1u << (SlotWeight * s)) * ((MaskWeight - Ctpop) << Cttz);
return Weight;
}
diff --git a/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
index 33da0ff31be8..ea4a25a62a0b 100644
--- a/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
+++ b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
@@ -43,7 +43,7 @@ void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
InstSeqLs &SeqLs) {
- unsigned Shamt = countTrailingZeros(Imm);
+ unsigned Shamt = llvm::countr_zero(Imm);
GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
AddInstr(SeqLs, Inst(SLL, Shamt));
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index a18787196bb5..4dee79add206 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -3405,7 +3405,7 @@ bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
}
// How many bits are in our mask?
- uint64_t NumBits = countTrailingOnes(MaskVal);
+ uint64_t NumBits = llvm::countr_one(MaskVal);
Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
@@ -3469,10 +3469,10 @@ bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
NumZeros = 0;
// The number of bits in the result bitfield will be the number of
// trailing ones (the AND) minus the number of bits we shift off
- NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
+ NumBits = llvm::countr_one(MaskVal) - ShiftAmt;
} else if (isShiftedMask_64(MaskVal)) {
- NumZeros = countTrailingZeros(MaskVal);
- unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
+ NumZeros = llvm::countr_zero(MaskVal);
+ unsigned NumOnes = llvm::countr_one(MaskVal >> NumZeros);
// The number of bits in the result bitfield will be the number of
// trailing zeros plus the number of set bits in the mask minus the
// number of bits we shift off
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 6de25b87016b..187563aafe39 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -334,7 +334,7 @@ struct PPCOperand : public MCParsedAsmOperand {
unsigned getCRBitMask() const {
assert(isCRBitMask() && "Invalid access!");
- return 7 - countTrailingZeros<uint64_t>(Imm.Val);
+ return 7 - llvm::countr_zero<uint64_t>(Imm.Val);
}
bool isToken() const override { return Kind == Token; }
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 21fee2441f32..1629f1b2810f 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -444,7 +444,7 @@ static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
const MCDisassembler *Decoder) {
// The cr bit encoding is 0x80 >> cr_reg_num.
- unsigned Zeros = countTrailingZeros(Imm);
+ unsigned Zeros = llvm::countr_zero(Imm);
assert(Zeros < 8 && "Invalid CR bit value");
Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index d737eec570eb..ef11a93f3152 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -266,8 +266,8 @@ bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
// For any 32 < Num < 64, check if the Imm contains at least Num consecutive
// zeros and return the number of bits by the left of these consecutive zeros.
static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
- uint32_t HiTZ = countTrailingZeros<uint32_t>(Hi_32(Imm));
- uint32_t LoLZ = countLeadingZeros<uint32_t>(Lo_32(Imm));
+ uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm));
+ uint32_t LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm));
if ((HiTZ + LoLZ) >= Num)
return (32 + HiTZ);
return 0;
@@ -280,10 +280,10 @@ std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I,
MachineRegisterInfo &MRI,
Register Reg,
uint64_t Imm) const {
- unsigned TZ = countTrailingZeros<uint64_t>(Imm);
- unsigned LZ = countLeadingZeros<uint64_t>(Imm);
- unsigned TO = countTrailingOnes<uint64_t>(Imm);
- unsigned LO = countLeadingOnes<uint64_t>(Imm);
+ unsigned TZ = llvm::countr_zero<uint64_t>(Imm);
+ unsigned LZ = llvm::countl_zero<uint64_t>(Imm);
+ unsigned TO = llvm::countr_one<uint64_t>(Imm);
+ unsigned LO = llvm::countl_one<uint64_t>(Imm);
uint32_t Hi32 = Hi_32(Imm);
uint32_t Lo32 = Lo_32(Imm);
uint32_t Shift = 0;
@@ -307,7 +307,7 @@ std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I,
assert(LZ < 64 && "Unexpected leading zeros here.");
// Count of ones follwing the leading zeros.
- unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ);
+ unsigned FO = llvm::countl_one<uint64_t>(Imm << LZ);
// 2-1) Patterns : {zeros}{31-bit value}
// {ones}{31-bit value}
if (isInt<32>(Imm)) {
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
index e4521aebad7e..3b9d5bc8f64d 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -60,17 +60,17 @@ static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
if (isShiftedMask_32(Val)) {
// look for the first non-zero bit
- MB = countLeadingZeros(Val);
+ MB = llvm::countl_zero(Val);
// look for the first zero bit after the run of ones
- ME = countLeadingZeros((Val - 1) ^ Val);
+ ME = llvm::countl_zero((Val - 1) ^ Val);
return true;
} else {
Val = ~Val; // invert mask
if (isShiftedMask_32(Val)) {
// effectively look for the first zero bit
- ME = countLeadingZeros(Val) - 1;
+ ME = llvm::countl_zero(Val) - 1;
// effectively look for the first one bit after the run of zeros
- MB = countLeadingZeros((Val - 1) ^ Val) + 1;
+ MB = llvm::countl_zero((Val - 1) ^ Val) + 1;
return true;
}
}
@@ -84,17 +84,17 @@ static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
if (isShiftedMask_64(Val)) {
// look for the first non-zero bit
- MB = countLeadingZeros(Val);
+ MB = llvm::countl_zero(Val);
// look for the first zero bit after the run of ones
- ME = countLeadingZeros((Val - 1) ^ Val);
+ ME = llvm::countl_zero((Val - 1) ^ Val);
return true;
} else {
Val = ~Val; // invert mask
if (isShiftedMask_64(Val)) {
// effectively look for the first zero bit
- ME = countLeadingZeros(Val) - 1;
+ ME = llvm::countl_zero(Val) - 1;
// effectively look for the first one bit after the run of zeros
- MB = countLeadingZeros((Val - 1) ^ Val) + 1;
+ MB = llvm::countl_zero((Val - 1) ^ Val) + 1;
return true;
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index be555ac0edf6..329a81970f64 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -2155,7 +2155,7 @@ unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
// If the value doesn't fit in 32 bits, see if we can shift it
// so that it fits in 32 bits.
if (!isInt<32>(Imm)) {
- Shift = countTrailingZeros<uint64_t>(Imm);
+ Shift = llvm::countr_zero<uint64_t>(Imm);
int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
if (isInt<32>(ImmSh))
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index d80a33ff6064..abf485545ff4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -926,8 +926,8 @@ static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
// For any 32 < Num < 64, check if the Imm contains at least Num consecutive
// zeros and return the number of bits by the left of these consecutive zeros.
static int findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
- unsigned HiTZ = countTrailingZeros<uint32_t>(Hi_32(Imm));
- unsigned LoLZ = countLeadingZeros<uint32_t>(Lo_32(Imm));
+ unsigned HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm));
+ unsigned LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm));
if ((HiTZ + LoLZ) >= Num)
return (32 + HiTZ);
return 0;
@@ -936,10 +936,10 @@ static int findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
// Direct materialization of 64-bit constants by enumerated patterns.
static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
uint64_t Imm, unsigned &InstCnt) {
- unsigned TZ = countTrailingZeros<uint64_t>(Imm);
- unsigned LZ = countLeadingZeros<uint64_t>(Imm);
- unsigned TO = countTrailingOnes<uint64_t>(Imm);
- unsigned LO = countLeadingOnes<uint64_t>(Imm);
+ unsigned TZ = llvm::countr_zero<uint64_t>(Imm);
+ unsigned LZ = llvm::countl_zero<uint64_t>(Imm);
+ unsigned TO = llvm::countr_one<uint64_t>(Imm);
+ unsigned LO = llvm::countl_one<uint64_t>(Imm);
unsigned Hi32 = Hi_32(Imm);
unsigned Lo32 = Lo_32(Imm);
SDNode *Result = nullptr;
@@ -967,7 +967,7 @@ static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
InstCnt = 2;
assert(LZ < 64 && "Unexpected leading zeros here.");
// Count of ones follwing the leading zeros.
- unsigned FO = countLeadingOnes<uint64_t>(Imm << LZ);
+ unsigned FO = llvm::countl_one<uint64_t>(Imm << LZ);
// 2-1) Patterns : {zeros}{31-bit value}
// {ones}{31-bit value}
if (isInt<32>(Imm)) {
@@ -1165,10 +1165,10 @@ static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
// were selected.
static SDNode *selectI64ImmDirectPrefix(SelectionDAG *CurDAG, const SDLoc &dl,
uint64_t Imm, unsigned &InstCnt) {
- unsigned TZ = countTrailingZeros<uint64_t>(Imm);
- unsigned LZ = countLeadingZeros<uint64_t>(Imm);
- unsigned TO = countTrailingOnes<uint64_t>(Imm);
- unsigned FO = countLeadingOnes<uint64_t>(LZ == 64 ? 0 : (Imm << LZ));
+ unsigned TZ = llvm::countr_zero<uint64_t>(Imm);
+ unsigned LZ = llvm::countl_zero<uint64_t>(Imm);
+ unsigned TO = llvm::countr_one<uint64_t>(Imm);
+ unsigned FO = llvm::countl_one<uint64_t>(LZ == 64 ? 0 : (Imm << LZ));
unsigned Hi32 = Hi_32(Imm);
unsigned Lo32 = Lo_32(Imm);
@@ -4872,7 +4872,7 @@ bool PPCDAGToDAGISel::tryAsPairOfRLDICL(SDNode *N) {
// wrapped run of ones, i.e.
// Change pattern |0001111100000011111111|
// to |1111111100000011111111|.
- unsigned NumOfLeadingZeros = countLeadingZeros(Imm64);
+ unsigned NumOfLeadingZeros = llvm::countl_zero(Imm64);
if (NumOfLeadingZeros != 0)
Imm64 |= maskLeadingOnes<uint64_t>(NumOfLeadingZeros);
@@ -4952,7 +4952,7 @@ bool PPCDAGToDAGISel::tryAsSingleRLDICL(SDNode *N) {
return false;
// If this is a 64-bit zero-extension mask, emit rldicl.
- unsigned MB = 64 - countTrailingOnes(Imm64);
+ unsigned MB = 64 - llvm::countr_one(Imm64);
unsigned SH = 0;
unsigned Imm;
SDValue Val = N->getOperand(0);
@@ -5002,7 +5002,7 @@ bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) {
// If this is a negated 64-bit zero-extension mask,
// i.e. the immediate is a sequence of ones from most significant side
// and all zero for reminder, we should use rldicr.
- unsigned MB = 63 - countTrailingOnes(~Imm64);
+ unsigned MB = 63 - llvm::countr_one(~Imm64);
unsigned SH = 0;
SDLoc dl(N);
SDValue Ops[] = {N->getOperand(0), getI32Imm(SH, dl), getI32Imm(MB, dl)};
@@ -5582,7 +5582,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
// If the multiplier fits int16, we can handle it with mulli.
int64_t Imm = cast<ConstantSDNode>(Op1)->getZExtValue();
- unsigned Shift = countTrailingZeros<uint64_t>(Imm);
+ unsigned Shift = llvm::countr_zero<uint64_t>(Imm);
if (isInt<16>(Imm) || !Shift)
break;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8031fe511cfd..2b33bd66a9f3 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -16929,7 +16929,7 @@ bool PPCTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
// 2. If the multiplier after shifted fits 16 bits, an extra shift
// instruction is needed than case 1, ie. MULLI and RLDICR
int64_t Imm = ConstNode->getSExtValue();
- unsigned Shift = countTrailingZeros<uint64_t>(Imm);
+ unsigned Shift = llvm::countr_zero<uint64_t>(Imm);
Imm >>= Shift;
if (isInt<16>(Imm))
return false;
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 7d3a8b4ca252..5d381a9540d9 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -193,7 +193,7 @@ static unsigned getKnownLeadingZeroCount(const unsigned Reg,
if (Opcode == PPC::ANDI_rec) {
uint16_t Imm = MI->getOperand(2).getImm();
- return 48 + countLeadingZeros(Imm);
+ return 48 + llvm::countl_zero(Imm);
}
if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 0c2bf9dad795..bc2f6683392c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -155,15 +155,15 @@ static void generateInstSeqImpl(int64_t Val,
static unsigned extractRotateInfo(int64_t Val) {
// for case: 0b111..1..xxxxxx1..1..
- unsigned LeadingOnes = countLeadingOnes((uint64_t)Val);
- unsigned TrailingOnes = countTrailingOnes((uint64_t)Val);
+ unsigned LeadingOnes = llvm::countl_one((uint64_t)Val);
+ unsigned TrailingOnes = llvm::countr_one((uint64_t)Val);
if (TrailingOnes > 0 && TrailingOnes < 64 &&
(LeadingOnes + TrailingOnes) > (64 - 12))
return 64 - TrailingOnes;
// for case: 0bxxx1..1..1...xxx
- unsigned UpperTrailingOnes = countTrailingOnes(Hi_32(Val));
- unsigned LowerLeadingOnes = countLeadingOnes(Lo_32(Val));
+ unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val));
+ unsigned LowerLeadingOnes = llvm::countl_one(Lo_32(Val));
if (UpperTrailingOnes < 32 &&
(UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
return 32 - UpperTrailingOnes;
@@ -180,7 +180,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
// or ADDIW. If there are trailing zeros, try generating a sign extended
// constant with no trailing zeros and use a final SLLI to restore them.
if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
- unsigned TrailingZeros = countTrailingZeros((uint64_t)Val);
+ unsigned TrailingZeros = llvm::countr_zero((uint64_t)Val);
int64_t ShiftedVal = Val >> TrailingZeros;
// If we can use C.LI+C.SLLI instead of LUI+ADDI(W) prefer that since
// its more compressible. But only if LUI+ADDI(W) isn't fusable.
@@ -202,7 +202,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
if (Val > 0 && Res.size() > 2) {
assert(ActiveFeatures[RISCV::Feature64Bit] &&
"Expected RV32 to only need 2 instructions");
- unsigned LeadingZeros = countLeadingZeros((uint64_t)Val);
+ unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
// Fill in the bits that will be shifted out with 1s. An example where this
// helps is trailing one masks with 32 or more ones. This will generate
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 994aa942b8df..80385ee28a20 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -728,7 +728,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
if (ShAmt <= 32 && isShiftedMask_64(Mask)) {
unsigned XLen = Subtarget->getXLen();
unsigned LeadingZeros = XLen - llvm::bit_width(Mask);
- unsigned TrailingZeros = countTrailingZeros(Mask);
+ unsigned TrailingZeros = llvm::countr_zero(Mask);
if (TrailingZeros > 0 && LeadingZeros == 32) {
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, VT, N0->getOperand(0),
@@ -757,7 +757,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
if (isShiftedMask_64(Mask) && N0.hasOneUse()) {
unsigned XLen = Subtarget->getXLen();
unsigned LeadingZeros = XLen - llvm::bit_width(Mask);
- unsigned TrailingZeros = countTrailingZeros(Mask);
+ unsigned TrailingZeros = llvm::countr_zero(Mask);
if (LeadingZeros == 32 && TrailingZeros > ShAmt) {
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, VT, N0->getOperand(0),
@@ -780,7 +780,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
Mask |= maskTrailingOnes<uint64_t>(ShAmt);
if (!isMask_64(Mask))
break;
- unsigned TrailingOnes = countTrailingOnes(Mask);
+ unsigned TrailingOnes = llvm::countr_one(Mask);
if (ShAmt >= TrailingOnes)
break;
// If the mask has 32 trailing ones, use SRLIW.
@@ -974,7 +974,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
// shifted mask with c2 leading zeros and c3 trailing zeros.
if (!LeftShift && isShiftedMask_64(C1)) {
unsigned Leading = XLen - llvm::bit_width(C1);
- unsigned Trailing = countTrailingZeros(C1);
+ unsigned Trailing = llvm::countr_zero(C1);
if (Leading == C2 && C2 + Trailing < XLen && OneUseOrZExtW &&
!IsCANDI) {
unsigned SrliOpc = RISCV::SRLI;
@@ -1012,7 +1012,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
// shifted mask with no leading zeros and c3 trailing zeros.
if (LeftShift && isShiftedMask_64(C1)) {
unsigned Leading = XLen - llvm::bit_width(C1);
- unsigned Trailing = countTrailingZeros(C1);
+ unsigned Trailing = llvm::countr_zero(C1);
if (Leading == 0 && C2 < Trailing && OneUseOrZExtW && !IsCANDI) {
SDNode *SRLI = CurDAG->getMachineNode(
RISCV::SRLI, DL, VT, X,
@@ -2191,7 +2191,7 @@ bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
// followed by a SHXADD with c3 for the X amount.
if (isShiftedMask_64(Mask)) {
unsigned Leading = XLen - llvm::bit_width(Mask);
- unsigned Trailing = countTrailingZeros(Mask);
+ unsigned Trailing = llvm::countr_zero(Mask);
if (LeftShift && Leading == 0 && C2 < Trailing && Trailing == ShAmt) {
SDLoc DL(N);
EVT VT = N.getValueType();
@@ -2229,7 +2229,7 @@ bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
unsigned C1 = N.getConstantOperandVal(1);
unsigned XLen = Subtarget->getXLen();
unsigned Leading = XLen - llvm::bit_width(Mask);
- unsigned Trailing = countTrailingZeros(Mask);
+ unsigned Trailing = llvm::countr_zero(Mask);
// Look for (shl (and X, Mask), C1) where Mask has 32 leading zeros and
// C3 trailing zeros. If C1+C3==ShAmt we can use SRLIW+SHXADD.
if (LeftShift && Leading == 32 && Trailing > 0 &&
@@ -2280,8 +2280,8 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
// 32-ShAmt leading zeros and c2 trailing zeros. We can use SLLI by
// c2-ShAmt followed by SHXADD_UW with ShAmt for the X amount.
if (isShiftedMask_64(Mask)) {
- unsigned Leading = countLeadingZeros(Mask);
- unsigned Trailing = countTrailingZeros(Mask);
+ unsigned Leading = llvm::countl_zero(Mask);
+ unsigned Trailing = llvm::countr_zero(Mask);
if (Leading == 32 - ShAmt && Trailing == C2 && Trailing > ShAmt) {
SDLoc DL(N);
EVT VT = N.getValueType();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5bb7beeff559..f09a1ab972f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -452,13 +452,13 @@ def AddiPairImmLarge : SDNodeXForm<imm, [{
}]>;
def TrailingZeros : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(countTrailingZeros(N->getZExtValue()),
+ return CurDAG->getTargetConstant(llvm::countr_zero(N->getZExtValue()),
SDLoc(N), N->getValueType(0));
}]>;
def XLenSubTrailingOnes : SDNodeXForm<imm, [{
uint64_t XLen = Subtarget->getXLen();
- uint64_t TrailingOnes = countTrailingOnes(N->getZExtValue());
+ uint64_t TrailingOnes = llvm::countr_one(N->getZExtValue());
return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
N->getValueType(0));
}]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 1a0ad8098b43..cf903570b7b0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -66,13 +66,13 @@ def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
def BCLRXForm : SDNodeXForm<imm, [{
// Find the lowest 0.
- return CurDAG->getTargetConstant(countTrailingOnes(N->getZExtValue()),
+ return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()),
SDLoc(N), N->getValueType(0));
}]>;
def SingleBitSetMaskToIndex : SDNodeXForm<imm, [{
// Find the lowest 1.
- return CurDAG->getTargetConstant(countTrailingZeros(N->getZExtValue()),
+ return CurDAG->getTargetConstant(llvm::countr_zero(N->getZExtValue()),
SDLoc(N), N->getValueType(0));
}]>;
@@ -104,7 +104,7 @@ def BSETINVTwoBitsMask : PatLeaf<(imm), [{
def BSETINVTwoBitsMaskHigh : SDNodeXForm<imm, [{
uint64_t I = N->getZExtValue();
- return CurDAG->getTargetConstant(63 - countLeadingZeros(I), SDLoc(N),
+ return CurDAG->getTargetConstant(63 - llvm::countl_zero(I), SDLoc(N),
N->getValueType(0));
}]>;
@@ -138,7 +138,7 @@ def BCLRITwoBitsMask : PatLeaf<(imm), [{
}]>;
def BCLRITwoBitsMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(countTrailingZeros(~N->getZExtValue()),
+ return CurDAG->getTargetConstant(llvm::countr_zero(~N->getZExtValue()),
SDLoc(N), N->getValueType(0));
}]>;
@@ -146,7 +146,7 @@ def BCLRITwoBitsMaskHigh : SDNodeXForm<imm, [{
uint64_t I = N->getSExtValue();
if (!Subtarget->is64Bit())
I |= 0xffffffffull << 32;
- return CurDAG->getTargetConstant(63 - countLeadingZeros(~I), SDLoc(N),
+ return CurDAG->getTargetConstant(63 - llvm::countl_zero(~I), SDLoc(N),
N->getValueType(0));
}]>;
@@ -248,7 +248,7 @@ def Shifted32OnesMask : PatLeaf<(imm), [{
if (!isShiftedMask_64(Imm))
return false;
- unsigned TrailingZeros = countTrailingZeros(Imm);
+ unsigned TrailingZeros = llvm::countr_zero(Imm);
return TrailingZeros > 0 && TrailingZeros < 32 &&
Imm == UINT64_C(0xFFFFFFFF) << TrailingZeros;
}], TrailingZeros>;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index aad0cf8faef2..fcc88d6d4682 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -87,7 +87,7 @@ static bool canUseShiftPair(Instruction *Inst, const APInt &Imm) {
// (and (shl x, c2), c1) will be matched to (srli (slli x, c2+c3), c3) if c1
// is a mask shifted by c2 bits with c3 leading zeros.
if (isShiftedMask_64(Mask)) {
- unsigned Trailing = countTrailingZeros(Mask);
+ unsigned Trailing = llvm::countr_zero(Mask);
if (ShAmt == Trailing)
return true;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 7590befa1a1b..c83c0d80fbc6 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2535,9 +2535,9 @@ static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
return 0;
// Work out the masks for the lowest and highest bits.
- unsigned HighShift = 63 - countLeadingZeros(Mask);
+ unsigned HighShift = 63 - llvm::countl_zero(Mask);
uint64_t High = uint64_t(1) << HighShift;
- uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
+ uint64_t Low = uint64_t(1) << llvm::countr_zero(Mask);
// Signed ordered comparisons are effectively unsigned if the sign
// bit is dropped.
diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h
index ded0460f97d6..e82cb1901633 100644
--- a/llvm/lib/Target/VE/VE.h
+++ b/llvm/lib/Target/VE/VE.h
@@ -451,8 +451,8 @@ inline static uint64_t val2MImm(uint64_t Val) {
if (Val == 0)
return 0; // (0)1
if (Val & (UINT64_C(1) << 63))
- return countLeadingOnes(Val); // (m)1
- return countLeadingZeros(Val) | 0x40; // (m)0
+ return llvm::countl_one(Val); // (m)1
+ return llvm::countl_zero(Val) | 0x40; // (m)0
}
/// mimm2Val - Convert a target MImm immediate to an integer immediate value.
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 699e83c6fe1e..7513b198e604 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -931,8 +931,8 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
// Produce implicit-defs for free by using killed registers.
while (Kills && Defs) {
- unsigned KReg = countTrailingZeros(Kills);
- unsigned DReg = countTrailingZeros(Defs);
+ unsigned KReg = llvm::countr_zero(Kills);
+ unsigned DReg = llvm::countr_zero(Defs);
LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg
<< "\n");
std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
@@ -956,7 +956,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
// Manually kill the rest.
while (Kills) {
- unsigned KReg = countTrailingZeros(Kills);
+ unsigned KReg = llvm::countr_zero(Kills);
LLVM_DEBUG(dbgs() << "Killing %fp" << KReg << "\n");
freeStackSlotBefore(I, KReg);
Kills &= ~(1 << KReg);
@@ -964,7 +964,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
// Load zeros for all the imp-defs.
while(Defs) {
- unsigned DReg = countTrailingZeros(Defs);
+ unsigned DReg = llvm::countr_zero(Defs);
LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
pushReg(DReg);
@@ -1047,7 +1047,7 @@ void FPS::handleCall(MachineBasicBlock::iterator &I) {
if (!ClobbersFPStack)
return;
- unsigned N = countTrailingOnes(STReturns);
+ unsigned N = llvm::countr_one(STReturns);
// FP registers used for function return must be consecutive starting at
// FP0
@@ -1634,14 +1634,14 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
if (STUses && !isMask_32(STUses))
MI.emitError("fixed input regs must be last on the x87 stack");
- unsigned NumSTUses = countTrailingOnes(STUses);
+ unsigned NumSTUses = llvm::countr_one(STUses);
// Defs must be contiguous from the stack top. ST0-STn.
if (STDefs && !isMask_32(STDefs)) {
MI.emitError("output regs must be last on the x87 stack");
STDefs = NextPowerOf2(STDefs) - 1;
}
- unsigned NumSTDefs = countTrailingOnes(STDefs);
+ unsigned NumSTDefs = llvm::countr_one(STDefs);
// So must the clobbered stack slots. ST0-STm, m >= n.
if (STClobbers && !isMask_32(STDefs | STClobbers))
@@ -1651,7 +1651,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
unsigned STPopped = STUses & (STDefs | STClobbers);
if (STPopped && !isMask_32(STPopped))
MI.emitError("implicitly popped regs must be last on the x87 stack");
- unsigned NumSTPopped = countTrailingOnes(STPopped);
+ unsigned NumSTPopped = llvm::countr_one(STPopped);
LLVM_DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
<< NumSTPopped << ", and defines " << NumSTDefs
@@ -1727,7 +1727,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
// Note: this might be a non-optimal pop sequence. We might be able to do
// better by trying to pop in stack order or something.
while (FPKills) {
- unsigned FPReg = countTrailingZeros(FPKills);
+ unsigned FPReg = llvm::countr_zero(FPKills);
if (isLive(FPReg))
freeStackSlotAfter(Inst, FPReg);
FPKills &= ~(1U << FPReg);
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 249ff21f5b0e..e7aea3326e5e 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2054,8 +2054,8 @@ static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
return true;
unsigned ShiftAmt = Shift.getConstantOperandVal(1);
- unsigned MaskLZ = countLeadingZeros(Mask);
- unsigned MaskTZ = countTrailingZeros(Mask);
+ unsigned MaskLZ = llvm::countl_zero(Mask);
+ unsigned MaskTZ = llvm::countr_zero(Mask);
// The amount of shift we're trying to fit into the addressing mode is taken
// from the trailing zeros of the mask.
@@ -2066,7 +2066,8 @@ static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
if (AMShiftAmt == 0 || AMShiftAmt > 3) return true;
// We also need to ensure that mask is a continuous run of bits.
- if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
+ if (llvm::countr_one(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64)
+ return true;
// Scale the leading zero count down based on the actual size of the value.
// Also scale it down based on the size of the shift.
@@ -2154,7 +2155,7 @@ static bool foldMaskedShiftToBEXTR(SelectionDAG &DAG, SDValue N,
// The amount of shift we're trying to fit into the addressing mode is taken
// from the trailing zeros of the mask.
- unsigned AMShiftAmt = countTrailingZeros(Mask);
+ unsigned AMShiftAmt = llvm::countr_zero(Mask);
// There is nothing we can do here unless the mask is removing some bits.
// Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
@@ -5650,8 +5651,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned SubRegIdx;
MVT SubRegVT;
unsigned TestOpcode;
- unsigned LeadingZeros = countLeadingZeros(Mask);
- unsigned TrailingZeros = countTrailingZeros(Mask);
+ unsigned LeadingZeros = llvm::countl_zero(Mask);
+ unsigned TrailingZeros = llvm::countr_zero(Mask);
// With leading/trailing zeros, the transform is profitable if we can
// eliminate a movabsq or shrink a 32-bit immediate to 8-bit without
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6a41f24151e5..6884ca1e776f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -31656,7 +31656,7 @@ void X86TargetLowering::emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const {
BitTest = Intrinsic::getDeclaration(AI->getModule(), IID_C, AI->getType());
- unsigned Imm = countTrailingZeros(C->getZExtValue());
+ unsigned Imm = llvm::countr_zero(C->getZExtValue());
Result = Builder.CreateCall(BitTest, {Addr, Builder.getInt8(Imm)});
} else {
BitTest = Intrinsic::getDeclaration(AI->getModule(), IID_I, AI->getType());
@@ -40184,8 +40184,8 @@ static SDValue combineX86ShufflesRecursively(
assert(isPowerOf2_32(RootMask.size()) &&
"Non-power-of-2 shuffle mask sizes");
assert(isPowerOf2_32(OpMask.size()) && "Non-power-of-2 shuffle mask sizes");
- unsigned RootMaskSizeLog2 = countTrailingZeros(RootMask.size());
- unsigned OpMaskSizeLog2 = countTrailingZeros(OpMask.size());
+ unsigned RootMaskSizeLog2 = llvm::countr_zero(RootMask.size());
+ unsigned OpMaskSizeLog2 = llvm::countr_zero(OpMask.size());
unsigned MaskWidth = std::max<unsigned>(OpMask.size(), RootMask.size());
unsigned RootRatio =
@@ -40197,8 +40197,8 @@ static SDValue combineX86ShufflesRecursively(
assert(isPowerOf2_32(MaskWidth) && "Non-power-of-2 shuffle mask sizes");
assert(isPowerOf2_32(RootRatio) && "Non-power-of-2 shuffle mask sizes");
assert(isPowerOf2_32(OpRatio) && "Non-power-of-2 shuffle mask sizes");
- unsigned RootRatioLog2 = countTrailingZeros(RootRatio);
- unsigned OpRatioLog2 = countTrailingZeros(OpRatio);
+ unsigned RootRatioLog2 = llvm::countr_zero(RootRatio);
+ unsigned OpRatioLog2 = llvm::countr_zero(OpRatio);
Mask.resize(MaskWidth, SM_SentinelUndef);
@@ -47318,7 +47318,7 @@ static SDValue combineMulSpecial(uint64_t MulAmt, SDNode *N, SelectionDAG &DAG,
// count how many zeros are up to the first bit.
// TODO: We can do this even without LEA at a cost of two shifts and an add.
if (isPowerOf2_64(MulAmt & (MulAmt - 1))) {
- unsigned ScaleShift = countTrailingZeros(MulAmt);
+ unsigned ScaleShift = llvm::countr_zero(MulAmt);
if (ScaleShift >= 1 && ScaleShift < 4) {
unsigned ShiftAmt = Log2_64((MulAmt & (MulAmt - 1)));
SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index f26b6d7a588a..3012035af11a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2634,11 +2634,11 @@ let Predicates = [HasBMI2], Defs = [EFLAGS] in {
def CountTrailingOnes : SDNodeXForm<imm, [{
// Count the trailing ones in the immediate.
- return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
+ return getI8Imm(llvm::countr_one(N->getZExtValue()), SDLoc(N));
}]>;
def BEXTRMaskXForm : SDNodeXForm<imm, [{
- unsigned Length = countTrailingOnes(N->getZExtValue());
+ unsigned Length = llvm::countr_one(N->getZExtValue());
return getI32Imm(Length << 8, SDLoc(N));
}]>;
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