[PATCH] D142612: [RISCV][NFC] Add test for register coalescing x0

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 492701.
luke added a comment.

Simplify test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142612/new/

https://reviews.llvm.org/D142612

Files:
  llvm/test/CodeGen/RISCV/regcoal-constreg.mir


Index: llvm/test/CodeGen/RISCV/regcoal-constreg.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/regcoal-constreg.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=simple-register-coalescing %s -o - | FileCheck %s
+---
+name: func
+registers:
+  - { id: 0, class: gpr }
+body: |
+  ; CHECK-LABEL: name: func
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT:   BEQ $x1, $x2, %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   PseudoRET implicit [[COPY1]]
+  bb.0:
+    %0 = COPY $x0
+    BEQ $x1, $x2, %bb.2
+
+  bb.1:
+    %0 = COPY $x0
+
+  bb.2:
+    PseudoRET implicit %0
+
+...


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