[PATCH] D136157: [X86][2/2] Support PREFETCHI instructions

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:36987
+    // PREFETCHIT0/1 apply when in 64-bit mode with RIP-relative addressing.
+    // They stay NOPs otherwise, so optimize them to PREFETCHT0/1.
+    if (MI.getOperand(0).getReg() != X86::RIP)
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Is this actually an optimization? IIRC there are some micro-arch where data can't both be in icache and dcache so this might have a flushing affect.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136157/new/

https://reviews.llvm.org/D136157