[PATCH] D142656: [SVE][codegen] Add pattern for SVE multiply-add accumulate

[Sushant Gokhale via Phabricator via llvm-commits]

sushgokh created this revision.
sushgokh added reviewers: SjoerdMeijer, dmgreen, david-arm, madhur13490.
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It has been observed for multiple SVE code samples that multiply-add IR pattern doesn't get realised into multiply-add accumulate instructions post instruction selection. This patch tries to add instruction selection pattern to improve this scenario.

The patch aims at:

1. Try to generate multiply-accumulate instructions post-isel at more places
2. Improving the current functionality of 'mad' instruction(which only kicks in if intrinsic is used)
3. with 'mla' instruction, it has been observed at multiple places that it generates extra register moves especially if the added is constant. This patch aims to improve this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142656

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
  llvm/test/CodeGen/AArch64/sve-gep.ll
  llvm/test/CodeGen/AArch64/sve-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-multiply-add-accumulate.ll

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