[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

[Luís Marques via Phabricator via llvm-commits]

luismarques accepted this revision.
luismarques added a comment.

LGTM, with some in-line caveats.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:1
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -----*- tablegen -*-===//
+//
----------------
`Zc` -> `Zc*`


================
Comment at: llvm/test/MC/RISCV/rv32zcb-valid.s:21
+# CHECK-ASM: encoding: [0x61,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened format for basic bit manipulation instructions){{$}}
+c.zext.b s0
----------------
Still has the old message phrasing with the "shortened".


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131141/new/

https://reviews.llvm.org/D131141