[PATCH] D142641: AMDGPU: Force sign operand of f64 fcopysign to f32

[Matt Arsenault via Phabricator via llvm-commits]

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The fcopysign DAG operation, unlike the IR one, allows
different types for the sign and magnitude. We can reduce
the bitwidth of the high operand since only the sign bit matters.

      

The default combine only introduces mixed fcopysign
operand types from fpext/fptrunc. We effectively do this
already during selection, but doing it earlier in the combiner
should expose new combine opportunities (e.g. the existing tests
now eliminate the load of the low half of the double). Unfortunately
this isn't enough to handle the case I'm interested in just yet.


https://reviews.llvm.org/D142641

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
  llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll

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