[llvm] 0c64e1b - [SelectionDAG] Add pcsections recursively on SDNode values
Marco Elver via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 26 07:15:32 PST 2023
Author: Martin Fink
Date: 2023-01-26T16:13:46+01:00
New Revision: 0c64e1b68f36640ffe82fc90e6279c50617ad1cc
URL: https://github.com/llvm/llvm-project/commit/0c64e1b68f36640ffe82fc90e6279c50617ad1cc
DIFF: https://github.com/llvm/llvm-project/commit/0c64e1b68f36640ffe82fc90e6279c50617ad1cc.diff
LOG: [SelectionDAG] Add pcsections recursively on SDNode values
When adding pcsections to SDNodes, recursively add them to all values of
the node as well.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D141048
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/pcsections.ll
llvm/test/CodeGen/X86/pcsections.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index aa1936c2757e7..661fa9332bafd 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2263,7 +2263,8 @@ class SelectionDAG {
}
/// Set PCSections to be associated with Node.
void addPCSections(const SDNode *Node, MDNode *MD) {
- SDEI[Node].PCSections = MD;
+ SmallPtrSet<const llvm::SDNode *, 32> Visited;
+ addPCSections(Node, MD, Visited);
}
/// Return PCSections associated with Node, or nullptr if none exists.
MDNode *getPCSections(const SDNode *Node) const {
@@ -2341,6 +2342,10 @@ class SelectionDAG {
SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,
void *&InsertPos);
+ /// Recursively set PCSections to be associated with Node and all its values.
+ void addPCSections(const SDNode *Node, MDNode *MD,
+ SmallPtrSet<const llvm::SDNode *, 32> &Visited);
+
/// Maps to auto-CSE operations.
std::vector<CondCodeSDNode*> CondCodeNodes;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 9a3609bc183bf..3f83fd843438e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1363,6 +1363,19 @@ SDNode *SelectionDAG::FindNodeOrInsertPos(const FoldingSetNodeID &ID,
return N;
}
+void SelectionDAG::addPCSections(
+ const SDNode *Node, MDNode *MD,
+ SmallPtrSet<const llvm::SDNode *, 32> &Visited) {
+ // If we've been here before, return now.
+ if (!Visited.insert(Node).second)
+ return;
+
+ SDEI[Node].PCSections = MD;
+
+ for (const SDValue &Op : Node->op_values())
+ addPCSections(Op.getNode(), MD, Visited);
+}
+
void SelectionDAG::clear() {
allnodes_clear();
OperandRecycler.clear(OperandAllocator);
diff --git a/llvm/test/CodeGen/AArch64/pcsections.ll b/llvm/test/CodeGen/AArch64/pcsections.ll
index 8d09c0165c8e1..4124d9ef41a41 100644
--- a/llvm/test/CodeGen/AArch64/pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/pcsections.ll
@@ -2,7 +2,7 @@
; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,DEFCM
-; RUN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPT,LARGE
+; RUN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
target triple = "aarch64-unknown-linux-gnu"
@@ -14,24 +14,61 @@ define i64 @multiple() !pcsections !0 {
; CHECK: .Lfunc_begin0:
; CHECK: // %bb.0: // %entry
; CHECK: .Lpcsection0:
+; --
+; LARGE-NEXT: movz
+; LARGE: .Lpcsection1:
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection2:
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection3:
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection4:
+; --
; CHECK-NEXT: ldr
; CHECK-NEXT: ret
; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base0:
+; --
+; DEFCM-NEXT: .Lpcsection_base0:
; DEFCM-NEXT: .word .Lfunc_begin0-.Lpcsection_base0
-; LARGE-NEXT: .xword .Lfunc_begin0-.Lpcsection_base0
-; CHECK-NEXT: .word .Lfunc_end0-.Lfunc_begin0
-; CHECK-NEXT: .section section_aux_42,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base1:
+; DEFCM-NEXT: .word .Lfunc_end0-.Lfunc_begin0
+; DEFCM-NEXT: .section section_aux_42,"awo", at progbits,.text
+; DEFCM-NEXT: .Lpcsection_base1:
; DEFCM-NEXT: .word .Lpcsection0-.Lpcsection_base1
-; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base1
-; CHECK-NEXT: .word 42
-; CHECK-NEXT: .section section_aux_21264,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base2:
+; DEFCM-NEXT: .word 42
+; DEFCM-NEXT: .section section_aux_21264,"awo", at progbits,.text
+; DEFCM-NEXT: .Lpcsection_base2:
; DEFCM-NEXT: .word .Lpcsection0-.Lpcsection_base2
-; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base2
-; CHECK-NEXT: .word 21264
-; CHECK-NEXT: .text
+; DEFCM-NEXT: .word 21264
+; --
+; LARGE-NEXT: .Lpcsection_base0:
+; LARGE-NEXT: .xword .Lfunc_begin0-.Lpcsection_base0
+; LARGE-NEXT: .word .Lfunc_end0-.Lfunc_begin0
+; LARGE-NEXT: .section section_aux_42,"awo", at progbits,.text
+; LARGE-NEXT: .Lpcsection_base1:
+; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base1
+; LARGE-NEXT: .Lpcsection_base2:
+; LARGE-NEXT: .xword .Lpcsection1-.Lpcsection_base2
+; LARGE-NEXT: .Lpcsection_base3:
+; LARGE-NEXT: .xword .Lpcsection2-.Lpcsection_base3
+; LARGE-NEXT: .Lpcsection_base4:
+; LARGE-NEXT: .xword .Lpcsection3-.Lpcsection_base4
+; LARGE-NEXT: .Lpcsection_base5:
+; LARGE-NEXT: .xword .Lpcsection4-.Lpcsection_base5
+; LARGE-NEXT: .word 42
+; LARGE-NEXT: .section section_aux_21264,"awo", at progbits,.text
+; LARGE-NEXT: .Lpcsection_base6:
+; LARGE-NEXT: .xword .Lpcsection0-.Lpcsection_base6
+; LARGE-NEXT: .Lpcsection_base7:
+; LARGE-NEXT: .xword .Lpcsection1-.Lpcsection_base7
+; LARGE-NEXT: .Lpcsection_base8:
+; LARGE-NEXT: .xword .Lpcsection2-.Lpcsection_base8
+; LARGE-NEXT: .Lpcsection_base9:
+; LARGE-NEXT: .xword .Lpcsection3-.Lpcsection_base9
+; LARGE-NEXT: .Lpcsection_base10:
+; LARGE-NEXT: .xword .Lpcsection4-.Lpcsection_base10
+; LARGE-NEXT: .word 21264
+; --
+; CHECK-NEXT: .text
entry:
%0 = load i64, ptr @bar, align 8, !pcsections !1
ret i64 %0
@@ -39,16 +76,46 @@ entry:
define i64 @test_simple_atomic() {
; CHECK-LABEL: test_simple_atomic:
-; CHECK: .Lpcsection1:
-; CHECK-NEXT: ldr
-; CHECK-NOT: .Lpcsection2
-; CHECK: ldr
+; --
+; DEFCM: .Lpcsection1:
+; DEFCM-NEXT: ldr
+; DEFCM-NOT: .Lpcsection2
+; DEFCM: ldr
+; --
+; LARGE: .Lpcsection5:
+; LARGE-NEXT: movz
+; LARGE-NEXT: movz
+; LARGE: .Lpcsection6:
+; LARGE-NEXT: movk
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection7:
+; LARGE-NEXT: movk
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection8:
+; LARGE-NEXT: movk
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection9:
+; LARGE-NEXT: ldr
+; LARGE-NEXT: ldr
+; --
; CHECK: add
; CHECK-NEXT: ret
; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base3:
+; --
+; DEFCM-NEXT: .Lpcsection_base3:
; DEFCM-NEXT: .word .Lpcsection1-.Lpcsection_base3
-; LARGE-NEXT: .xword .Lpcsection1-.Lpcsection_base3
+; --
+; LARGE-NEXT: .Lpcsection_base11:
+; LARGE-NEXT: .xword .Lpcsection5-.Lpcsection_base11
+; LARGE-NEXT: .Lpcsection_base12:
+; LARGE-NEXT: .xword .Lpcsection6-.Lpcsection_base12
+; LARGE-NEXT: .Lpcsection_base13:
+; LARGE-NEXT: .xword .Lpcsection7-.Lpcsection_base13
+; LARGE-NEXT: .Lpcsection_base14:
+; LARGE-NEXT: .xword .Lpcsection8-.Lpcsection_base14
+; LARGE-NEXT: .Lpcsection_base15:
+; LARGE-NEXT: .xword .Lpcsection9-.Lpcsection_base15
+; --
; CHECK-NEXT: .text
entry:
%0 = load atomic i64, ptr @foo monotonic, align 8, !pcsections !0
@@ -84,23 +151,78 @@ define i64 @test_complex_atomic() {
; CHECK-UNOPT: .Lpcsection13:
; CHECK-UNOPT-NEXT: b
; ---
+; LARGE: .Lpcsection10:
+; LARGE-NEXT: movz
+; LARGE-NEXT: .Lpcsection11:
+; LARGE-NEXT: movk
+; LARGE-NEXT: .Lpcsection12:
+; LARGE-NEXT: movk
+; LARGE-NEXT: .Lpcsection13:
+; LARGE-NEXT: movk
+; LARGE: .Lpcsection14:
+; LARGE-NEXT: ldxr
+; LARGE-NEXT: .Lpcsection15:
+; LARGE-NEXT: add
+; LARGE-NEXT: .Lpcsection16:
+; LARGE-NEXT: stxr
+; LARGE-NEXT: .Lpcsection17:
+; LARGE-NEXT: cbnz
+; ---
; CHECK-NOT: .Lpcsection
; CHECK: ldr
; CHECK: ret
; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base4:
-; DEFCM-NEXT: .word .Lpcsection2-.Lpcsection_base4
-; LARGE-NEXT: .xword .Lpcsection2-.Lpcsection_base4
-; CHECK-NEXT: .Lpcsection_base5:
-; DEFCM-NEXT: .word .Lpcsection3-.Lpcsection_base5
-; LARGE-NEXT: .xword .Lpcsection3-.Lpcsection_base5
-; CHECK-NEXT: .Lpcsection_base6:
-; DEFCM-NEXT: .word .Lpcsection4-.Lpcsection_base6
-; LARGE-NEXT: .xword .Lpcsection4-.Lpcsection_base6
-; CHECK-NEXT: .Lpcsection_base7:
-; DEFCM-NEXT: .word .Lpcsection5-.Lpcsection_base7
-; LARGE-NEXT: .xword .Lpcsection5-.Lpcsection_base7
-; CHECK-UNOPT: .word .Lpcsection13-.Lpcsection_base15
+; ---
+; CHECK-OPT-NEXT: .Lpcsection_base4:
+; CHECK-OPT-NEXT: .word .Lpcsection2-.Lpcsection_base4
+; CHECK-OPT-NEXT: .Lpcsection_base5:
+; CHECK-OPT-NEXT: .word .Lpcsection3-.Lpcsection_base5
+; CHECK-OPT-NEXT: .Lpcsection_base6:
+; CHECK-OPT-NEXT: .word .Lpcsection4-.Lpcsection_base6
+; CHECK-OPT-NEXT: .Lpcsection_base7:
+; CHECK-OPT-NEXT: .word .Lpcsection5-.Lpcsection_base7
+; ---
+; CHECK-UNOPT-NEXT: .Lpcsection_base4:
+; CHECK-UNOPT-NEXT: .word .Lpcsection2-.Lpcsection_base4
+; CHECK-UNOPT-NEXT: .Lpcsection_base5:
+; CHECK-UNOPT-NEXT: .word .Lpcsection3-.Lpcsection_base5
+; CHECK-UNOPT-NEXT: .Lpcsection_base6:
+; CHECK-UNOPT-NEXT: .word .Lpcsection4-.Lpcsection_base6
+; CHECK-UNOPT-NEXT: .Lpcsection_base7:
+; CHECK-UNOPT-NEXT: .word .Lpcsection5-.Lpcsection_base7
+; CHECK-UNOPT-NEXT: .Lpcsection_base8:
+; CHECK-UNOPT-NEXT: .word .Lpcsection6-.Lpcsection_base8
+; CHECK-UNOPT-NEXT: .Lpcsection_base9:
+; CHECK-UNOPT-NEXT: .word .Lpcsection7-.Lpcsection_base9
+; CHECK-UNOPT-NEXT: .Lpcsection_base10:
+; CHECK-UNOPT-NEXT: .word .Lpcsection8-.Lpcsection_base10
+; CHECK-UNOPT-NEXT: .Lpcsection_base11:
+; CHECK-UNOPT-NEXT: .word .Lpcsection9-.Lpcsection_base11
+; CHECK-UNOPT-NEXT: .Lpcsection_base12:
+; CHECK-UNOPT-NEXT: .word .Lpcsection10-.Lpcsection_base12
+; CHECK-UNOPT-NEXT: .Lpcsection_base13:
+; CHECK-UNOPT-NEXT: .word .Lpcsection11-.Lpcsection_base13
+; CHECK-UNOPT-NEXT: .Lpcsection_base14:
+; CHECK-UNOPT-NEXT: .word .Lpcsection12-.Lpcsection_base14
+; CHECK-UNOPT-NEXT: .Lpcsection_base15:
+; CHECK-UNOPT-NEXT: .word .Lpcsection13-.Lpcsection_base15
+; ---
+; LARGE-NEXT: .Lpcsection_base16:
+; LARGE-NEXT: .xword .Lpcsection10-.Lpcsection_base16
+; LARGE-NEXT: .Lpcsection_base17:
+; LARGE-NEXT: .xword .Lpcsection11-.Lpcsection_base17
+; LARGE-NEXT: .Lpcsection_base18:
+; LARGE-NEXT: .xword .Lpcsection12-.Lpcsection_base18
+; LARGE-NEXT: .Lpcsection_base19:
+; LARGE-NEXT: .xword .Lpcsection13-.Lpcsection_base19
+; LARGE-NEXT: .Lpcsection_base20:
+; LARGE-NEXT: .xword .Lpcsection14-.Lpcsection_base20
+; LARGE-NEXT: .Lpcsection_base21:
+; LARGE-NEXT: .xword .Lpcsection15-.Lpcsection_base21
+; LARGE-NEXT: .Lpcsection_base22:
+; LARGE-NEXT: .xword .Lpcsection16-.Lpcsection_base22
+; LARGE-NEXT: .Lpcsection_base23:
+; LARGE-NEXT: .xword .Lpcsection17-.Lpcsection_base23
; CHECK-NEXT: .text
entry:
%0 = atomicrmw add ptr @foo, i64 1 monotonic, align 8, !pcsections !0
diff --git a/llvm/test/CodeGen/X86/pcsections.ll b/llvm/test/CodeGen/X86/pcsections.ll
index fbcac484e8e9d..ca7d40fc66a56 100644
--- a/llvm/test/CodeGen/X86/pcsections.ll
+++ b/llvm/test/CodeGen/X86/pcsections.ll
@@ -48,25 +48,47 @@ define i64 @multiple() !pcsections !0 {
; CHECK-LABEL: multiple:
; CHECK-NEXT: .Lfunc_begin2
; CHECK: # %bb.0: # %entry
-; CHECK: .Lpcsection0:
-; CHECK-NEXT: movq
+; --
+; DEFCM: .Lpcsection0:
+; DEFCM-NEXT: movq
+; --
+; LARGE: .Lpcsection0:
+; LARGE-NEXT: movabsq
+; LARGE-NEXT: .Lpcsection1:
+; LARGE-NEXT: movq
+; --
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end2:
-; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base2:
-; DEFCM-NEXT: .long .Lfunc_begin2-.Lpcsection_base2
-; LARGE-NEXT: .quad .Lfunc_begin2-.Lpcsection_base2
-; CHECK-NEXT: .long .Lfunc_end2-.Lfunc_begin2
-; CHECK-NEXT: .section section_aux_42,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base3:
-; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base3
-; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base3
-; CHECK-NEXT: .long 42
-; CHECK-NEXT: .section section_aux_21264,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base4:
-; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base4
-; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base4
-; CHECK-NEXT: .long 21264
+; CHECK: .section section_no_aux,"awo", at progbits,.text
+; --
+; DEFCM-NEXT: .Lpcsection_base2:
+; DEFCM-NEXT: .long .Lfunc_begin2-.Lpcsection_base2
+; DEFCM-NEXT: .long .Lfunc_end2-.Lfunc_begin2
+; DEFCM-NEXT: .section section_aux_42,"awo", at progbits,.text
+; DEFCM-NEXT: .Lpcsection_base3:
+; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base3
+; DEFCM-NEXT: .long 42
+; DEFCM-NEXT: .section section_aux_21264,"awo", at progbits,.text
+; DEFCM-NEXT: .Lpcsection_base4:
+; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base4
+; DEFCM-NEXT: .long 21264
+; --
+; LARGE: .Lpcsection_base2:
+; LARGE-NEXT: .quad .Lfunc_begin2-.Lpcsection_base2
+; LARGE-NEXT: .long .Lfunc_end2-.Lfunc_begin2
+; LARGE-NEXT: .section section_aux_42,"awo", at progbits,.text
+; LARGE-NEXT: .Lpcsection_base3:
+; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base3
+; LARGE-NEXT: .Lpcsection_base4:
+; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base4
+; LARGE-NEXT: .long 42
+; LARGE-NEXT: .section section_aux_21264,"awo", at progbits,.text
+; LARGE-NEXT: .Lpcsection_base5:
+; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base5
+; LARGE-NEXT: .Lpcsection_base6:
+; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base6
+; LARGE-NEXT: .long 21264
+; --
; CHECK-NEXT: .text
entry:
%0 = load i64, ptr @bar, align 8, !pcsections !2
@@ -75,16 +97,29 @@ entry:
define i64 @test_simple_atomic() {
; CHECK-LABEL: test_simple_atomic:
-; CHECK: .Lpcsection1:
-; CHECK-NEXT: movq
+; --
+; DEFCM: .Lpcsection1:
+; DEFCM-NEXT: movq
+; --
+; LARGE: .Lpcsection2:
+; LARGE-NEXT: movabsq
+; LARGE-NEXT: .Lpcsection3:
+; LARGE-NEXT: movq
+; --
; CHECK-NOT: .Lpcsection
; CHECK: addq
; CHECK-NEXT: retq
; CHECK-NEXT: .Lfunc_end3:
-; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base5:
-; DEFCM-NEXT: .long .Lpcsection1-.Lpcsection_base5
-; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base5
+; CHECK: .section section_no_aux,"awo", at progbits,.text
+; --
+; DEFCM-NEXT: .Lpcsection_base5:
+; DEFCM-NEXT: .long .Lpcsection1-.Lpcsection_base5
+; --
+; LARGE-NEXT: .Lpcsection_base7:
+; LARGE-NEXT: .quad .Lpcsection2-.Lpcsection_base7
+; LARGE-NEXT: .Lpcsection_base8:
+; LARGE-NEXT: .quad .Lpcsection3-.Lpcsection_base8
+; --
; CHECK-NEXT: .text
entry:
%0 = load atomic i64, ptr @foo monotonic, align 8, !pcsections !0
@@ -95,18 +130,38 @@ entry:
define i64 @test_complex_atomic() {
; CHECK-LABEL: test_complex_atomic:
-; CHECK: movl $1
-; CHECK-NEXT: .Lpcsection2:
-; CHECK-NEXT: lock xaddq
+; --
+; DEFCM: .Lpcsection2:
+; DEFCM-NEXT: movl
+; DEFCM-NEXT: .Lpcsection3:
+; DEFCM-NEXT: lock
+; --
+; LARGE: .Lpcsection4:
+; LARGE-NEXT: movabsq
+; LARGE-NEXT: .Lpcsection5:
+; LARGE-NEXT: movl
+; LARGE-NEXT: .Lpcsection6:
+; LARGE-NEXT: lock
+; --
; CHECK-NOT: .Lpcsection
; CHECK: movq
; CHECK: addq
; CHECK: retq
; CHECK-NEXT: .Lfunc_end4:
-; CHECK: .section section_no_aux,"awo", at progbits,.text
-; CHECK-NEXT: .Lpcsection_base6:
-; DEFCM-NEXT: .long .Lpcsection2-.Lpcsection_base6
-; LARGE-NEXT: .quad .Lpcsection2-.Lpcsection_base6
+; CHECK: .section section_no_aux,"awo", at progbits,.text
+; --
+; DEFCM-NEXT: .Lpcsection_base6:
+; DEFCM-NEXT: .long .Lpcsection2-.Lpcsection_base6
+; DEFCM-NEXT: .Lpcsection_base7:
+; DEFCM-NEXT: .long .Lpcsection3-.Lpcsection_base7
+; --
+; LARGE-NEXT: .Lpcsection_base9:
+; LARGE-NEXT: .quad .Lpcsection4-.Lpcsection_base9
+; LARGE-NEXT: .Lpcsection_base10:
+; LARGE-NEXT: .quad .Lpcsection5-.Lpcsection_base10
+; LARGE-NEXT: .Lpcsection_base11:
+; LARGE-NEXT: .quad .Lpcsection6-.Lpcsection_base11
+; --
; CHECK-NEXT: .text
entry:
%0 = atomicrmw add ptr @foo, i64 1 monotonic, align 8, !pcsections !0
More information about the llvm-commits
mailing list