[PATCH] D142456: [AArch64][CostModel]: Add costs for zero/sign extend.
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 26 03:51:35 PST 2023
david-arm added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:2066
+ // where each operation has a cost of 1.
+ { ISD::ZERO_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 3},
+ { ISD::ZERO_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},
----------------
I think perhaps this can just be a cost of 2 because there are only 2 unpacks needed? Same for the SIGN_EXTEND case.
================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:2072
+ { ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 8},
+ { ISD::SIGN_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 16},
};
----------------
david-arm wrote:
> It would be good to complete the other extends from legal types here too, such as
>
> { ISD::ZERO_EXTEND, MVT::nxv8i32, MVT::nxv8i16, ?},
> { ISD::ZERO_EXTEND, MVT::nxv8i64, MVT::nxv8i16, ?},
> { ISD::ZERO_EXTEND, MVT::nxv4i64, MVT::nxv4i32, ?},
>
> { ISD::SIGN_EXTEND, MVT::nxv8i32, MVT::nxv8i16, ?},
> { ISD::SIGN_EXTEND, MVT::nxv8i64, MVT::nxv8i16, ?},
> { ISD::SIGN_EXTEND, MVT::nxv4i64, MVT::nxv4i32, ?},
Hi @hassnaa-arm, I think this patch is still missing the other extends that @sdesmalen and I suggested?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D142456/new/
https://reviews.llvm.org/D142456
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