[PATCH] D142466: [AArch64][SME2] Add multi-vector saturating rounding shift right intrinsics

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:138
+    : Pat<(out_vt (intrinsic in_vt:$Zn1, in_vt:$Zn2, (i32 imm_ty:$i))),
+                  (!cast<Instruction>(name) (REG_SEQUENCE ZPR2, in_vt:$Zn1, zsub0, in_vt:$Zn2, zsub1), imm_ty:$i)>;
+
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CarolineConcatto wrote:
> Kerry I have a glance and is it correct to assume that we should replace the ZPR4 and ZPR3 in   SME2_Sat_Shift_VG2_Pat and ZPR2Mul2 and  SME2_Sat_Shift_VG4_Pat by ZPR4Mul4
Thanks @CarolineConcatto, you're right that this should be ZPR2Mul2 & ZPR4Mul4. I've changed this and added an unused first argument to each of the tests to make sure the multi-vector lists start with a multiple of 2 or 4.


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-qrshr.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+sme2 -mattr=+bf16 -verify-machineinstrs < %s | FileCheck %s
+
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CarolineConcatto wrote:
> David asked me to remove-mattr=+sve from my tests, because it is not needed. Is it in yours?
It's not needed, I've removed unnecessary flags from this test and sve2p1-intrinsics-qrshr.ll.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142466/new/

https://reviews.llvm.org/D142466