[PATCH] D142456: [AArch64][CostModel]: Add costs for zero/sign extend.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D142456#4079499 <https://reviews.llvm.org/D142456#4079499>, @hassnaa-arm wrote:

> In D142456#4079434 <https://reviews.llvm.org/D142456#4079434>, @dmgreen wrote:
>
>>> where each operation has a cost of 2
>>
>> Why does each instruction have a cost of 2?
>
> Because that is mentioned here: https://developer.arm.com/documentation/pjdoc466751330-9685/latest/ 
> in section 3.25 (SVE integer instructions)

Hi @hassnaa-arm, the cost-model shouldn't be hardcoding the number of cycles for one specific micro-architecture, because the cost-model should be accurate for other micro-architectures as well.
The cost requested here is the througput cost, not the latency. The throughput is closer to the number of instructions that is required for the operation.


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