[PATCH] D142409: [RISCV][InsertVSETVLI] Handle partially transparent instructions in PRE
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 24 17:53:01 PST 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1197
+ // not make this change without reflowing later blocks as well.
+ // 2) If we don't actually remove a transition, inserting a vesetvli
+ // into the predecessor block would be correct, but unprofitable.
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vesetvli -> vsetvli
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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1201
+ VSETVLIInfo CurInfo = AvailableInfo;
+ int64_t TransitionsRemoved = 0;
+ for (const MachineInstr &MI : MBB) {
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Why int64_t as opposed to int?
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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll:959
; This case demonstrates a PRE oppurtunity where the first instruction
; in the block doesn't require a state transition. Essentially, we need
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opportunity*
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142409/new/
https://reviews.llvm.org/D142409
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