[PATCH] D142217: [MC] Store target Insts table in reverse order. NFC.

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG96f49905de25: [MC] Store target Insts table in reverse order. NFC. (authored by foad).

Changed prior to commit:
  https://reviews.llvm.org/D142217?vs=491474&id=491901#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142217/new/

https://reviews.llvm.org/D142217

Files:
  llvm/include/llvm/MC/MCInstrInfo.h
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/utils/TableGen/InstrInfoEmitter.cpp


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
===================================================================
--- llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -924,20 +924,19 @@
   Records.startTimer("Emit operand info");
   EmitOperandInfo(OS, OperandInfoIDs);
 
-  // Emit all of the MCInstrDesc records in their ENUM ordering.
-  //
+  // Emit all of the MCInstrDesc records in reverse ENUM ordering.
   Records.startTimer("Emit InstrDesc records");
   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
     Target.getInstructionsByEnumValue();
 
   SequenceToOffsetTable<std::string> InstrNames;
-  unsigned Num = 0;
-  for (const CodeGenInstruction *Inst : NumberedInstructions) {
+  unsigned Num = NumberedInstructions.size();
+  for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
     // Keep a list of the instruction names.
     InstrNames.add(std::string(Inst->TheDef->getName()));
     // Emit the record into the table.
-    emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
+    emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoIDs, OS);
   }
   OS << "};\n\n";
 
Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -2503,7 +2503,8 @@
       RegNum = 0;
     } else {
       unsigned NextOpIndex = Inst.getNumOperands();
-      const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
+      const MCInstrDesc &MCID =
+          ARMInsts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()];
       int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
       assert(TiedOp >= 0 &&
              "Inactive register in vpred_r is not tied to an output!");
Index: llvm/include/llvm/MC/MCInstrInfo.h
===================================================================
--- llvm/include/llvm/MC/MCInstrInfo.h
+++ llvm/include/llvm/MC/MCInstrInfo.h
@@ -30,7 +30,7 @@
                                                std::string &);
 
 private:
-  const MCInstrDesc *Desc;          // Raw array to allow static init'n
+  const MCInstrDesc *LastDesc;      // Raw array to allow static init'n
   const unsigned *InstrNameIndices; // Array for name indices in InstrNameData
   const char *InstrNameData;        // Instruction name string pool
   // Subtarget feature that an instruction is deprecated on, if any
@@ -48,7 +48,7 @@
   void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND,
                        const uint8_t *DF,
                        const ComplexDeprecationPredicate *CDI, unsigned NO) {
-    Desc = D;
+    LastDesc = D + NO - 1;
     InstrNameIndices = NI;
     InstrNameData = ND;
     DeprecatedFeatures = DF;
@@ -62,7 +62,8 @@
   /// specified instruction opcode.
   const MCInstrDesc &get(unsigned Opcode) const {
     assert(Opcode < NumOpcodes && "Invalid opcode!");
-    return Desc[Opcode];
+    // The table is indexed backwards from the last entry.
+    return *(LastDesc - Opcode);
   }
 
   /// Returns the name for the instructions with the given opcode.


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