[llvm] feea695 - [SCCP] Add vector add tests for nuw/nsw inference.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2023-01-24T14:14:28Z
New Revision: feea695653df9879027e63c3565434fcb2020fba

URL: https://github.com/llvm/llvm-project/commit/feea695653df9879027e63c3565434fcb2020fba
DIFF: https://github.com/llvm/llvm-project/commit/feea695653df9879027e63c3565434fcb2020fba.diff

LOG: [SCCP] Add vector add tests for nuw/nsw inference.

Also removes a dead argument from some tests.

Added: 
    

Modified: 
    llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll b/llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll
index 864760cb54558..6ab9c41c20f63 100644
--- a/llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll
+++ b/llvm/test/Transforms/SCCP/add-nuw-nsw-flags.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes=ipsccp -S %s | FileCheck %s
 
-define i8 @range_from_lshr(i8 %a, i8 %b) {
+define i8 @range_from_lshr(i8 %a) {
 ; CHECK-LABEL: @range_from_lshr(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_SHR:%.*]] = lshr i8 [[A:%.*]], 1
@@ -26,7 +26,7 @@ entry:
   ret i8 %res.3
 }
 
-define i8 @a_and_15_add_1(i8 %a, i8 %b) {
+define i8 @a_and_15_add_1(i8 %a) {
 ; CHECK-LABEL: @a_and_15_add_1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_AND:%.*]] = and i8 [[A:%.*]], 15
@@ -39,6 +39,32 @@ entry:
   ret i8 %add.1
 }
 
+define <4 x i8> @range_from_lshr_vec(<4 x i8> %a) {
+; CHECK-LABEL: @range_from_lshr_vec(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_SHR:%.*]] = lshr <4 x i8> [[A:%.*]], <i8 1, i8 2, i8 3, i8 4>
+; CHECK-NEXT:    [[ADD_1:%.*]] = add <4 x i8> [[A_SHR]], <i8 1, i8 2, i8 3, i8 4>
+; CHECK-NEXT:    ret <4 x i8> [[ADD_1]]
+;
+entry:
+  %a.shr = lshr <4 x i8> %a, <i8 1, i8 2, i8 3, i8 4>
+  %add.1 = add <4 x i8> %a.shr, <i8 1, i8 2, i8 3, i8 4>
+  ret <4 x i8> %add.1
+}
+
+define <4 x i8> @range_from_lshr_vec_2(<4 x i8> %a) {
+; CHECK-LABEL: @range_from_lshr_vec_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A_SHR:%.*]] = lshr <4 x i8> [[A:%.*]], <i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT:    [[ADD_1:%.*]] = add <4 x i8> [[A_SHR]], <i8 2, i8 2, i8 2, i8 2>
+; CHECK-NEXT:    ret <4 x i8> [[ADD_1]]
+;
+entry:
+  %a.shr = lshr <4 x i8> %a, <i8 1, i8 1, i8 1, i8 1>
+  %add.1 = add <4 x i8> %a.shr, <i8 2, i8 2, i8 2, i8 2>
+  ret <4 x i8> %add.1
+}
+
 define i8 @sge_0_and_sle_90(i8 %a) {
 ; CHECK-LABEL: @sge_0_and_sle_90(
 ; CHECK-NEXT:  entry: