[llvm] 8ea4a4b - [AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection Extension
Lucas Prates via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 23 07:00:57 PST 2023
Author: Lucas Prates
Date: 2023-01-23T15:00:51Z
New Revision: 8ea4a4b0f47a1feb2193f6eccd311b50f8a2a27a
URL: https://github.com/llvm/llvm-project/commit/8ea4a4b0f47a1feb2193f6eccd311b50f8a2a27a
DIFF: https://github.com/llvm/llvm-project/commit/8ea4a4b0f47a1feb2193f6eccd311b50f8a2a27a.diff
LOG: [AArch64] Add missing system register for v8.9-A/v9.4-A Permission Indirection Extension
This adds support for the missing `PIRE0_EL12` system register, part of
v8.9-A/v9.4-A's Permission Indirection Extension.
Patch by Son Tuan Vu.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D141400
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/basic-a64-instructions.s
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index f42942fc2a8e7..c7f404463c587 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1775,6 +1775,7 @@ def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>;
// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>;
def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>;
def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>;
def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>;
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index 43e69e2926461..b30a0c4b0af89 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -143,6 +143,7 @@ foo:
msr MAIR2_EL2, x3
msr MAIR2_EL3, x3
msr PIRE0_EL1, x3
+ msr PIRE0_EL12, x3
msr PIRE0_EL2, x3
msr PIR_EL1, x3
msr PIR_EL12, x3
@@ -250,6 +251,7 @@ foo:
; CHECK: msr MAIR2_EL2, x3 ; encoding: [0x23,0xa1,0x1c,0xd5]
; CHECK: msr MAIR2_EL3, x3 ; encoding: [0x23,0xa1,0x1e,0xd5]
; CHECK: msr PIRE0_EL1, x3 ; encoding: [0x43,0xa2,0x18,0xd5]
+; CHECK: msr PIRE0_EL12, x3 ; encoding: [0x43,0xa2,0x1d,0xd5]
; CHECK: msr PIRE0_EL2, x3 ; encoding: [0x43,0xa2,0x1c,0xd5]
; CHECK: msr PIR_EL1, x3 ; encoding: [0x63,0xa2,0x18,0xd5]
; CHECK: msr PIR_EL12, x3 ; encoding: [0x63,0xa2,0x1d,0xd5]
@@ -473,6 +475,7 @@ foo:
mrs x3, MAIR2_EL2
mrs x3, MAIR2_EL3
mrs x3, PIRE0_EL1
+ mrs x3, PIRE0_EL12
mrs x3, PIRE0_EL2
mrs x3, PIR_EL1
mrs x3, PIR_EL12
@@ -691,6 +694,7 @@ foo:
; CHECK: mrs x3, MAIR2_EL2 ; encoding: [0x23,0xa1,0x3c,0xd5]
; CHECK: mrs x3, MAIR2_EL3 ; encoding: [0x23,0xa1,0x3e,0xd5]
; CHECK: mrs x3, PIRE0_EL1 ; encoding: [0x43,0xa2,0x38,0xd5]
+; CHECK: mrs x3, PIRE0_EL12 ; encoding: [0x43,0xa2,0x3d,0xd5]
; CHECK: mrs x3, PIRE0_EL2 ; encoding: [0x43,0xa2,0x3c,0xd5]
; CHECK: mrs x3, PIR_EL1 ; encoding: [0x63,0xa2,0x38,0xd5]
; CHECK: mrs x3, PIR_EL12 ; encoding: [0x63,0xa2,0x3d,0xd5]
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index 51584abdb8e71..89f5944e02c51 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -3948,6 +3948,7 @@ _func:
msr MAIR2_EL2, x12
msr MAIR2_EL3, x12
msr PIRE0_EL1, x12
+ msr PIRE0_EL12, x12
msr PIRE0_EL2, x12
msr PIR_EL1, x12
msr PIR_EL12, x12
@@ -4229,6 +4230,7 @@ _func:
// CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12 // encoding: [0x2c,0xa1,0x1c,0xd5]
// CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12 // encoding: [0x2c,0xa1,0x1e,0xd5]
// CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12 // encoding: [0x4c,0xa2,0x18,0xd5]
+// CHECK: msr {{pire0_el12|PIRE0_EL12}}, x12 // encoding: [0x4c,0xa2,0x1d,0xd5]
// CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12 // encoding: [0x4c,0xa2,0x1c,0xd5]
// CHECK: msr {{pir_el1|PIR_EL1}}, x12 // encoding: [0x6c,0xa2,0x18,0xd5]
// CHECK: msr {{pir_el12|PIR_EL12}}, x12 // encoding: [0x6c,0xa2,0x1d,0xd5]
@@ -4566,6 +4568,7 @@ _func:
mrs x9, MAIR2_EL2
mrs x9, MAIR2_EL3
mrs x9, PIRE0_EL1
+ mrs x9, PIRE0_EL12
mrs x9, PIRE0_EL2
mrs x9, PIR_EL1
mrs x9, PIR_EL12
@@ -4902,6 +4905,7 @@ _func:
// CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}} // encoding: [0x29,0xa1,0x3c,0xd5]
// CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}} // encoding: [0x29,0xa1,0x3e,0xd5]
// CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}} // encoding: [0x49,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{pire0_el12|PIRE0_EL12}} // encoding: [0x49,0xa2,0x3d,0xd5]
// CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}} // encoding: [0x49,0xa2,0x3c,0xd5]
// CHECK: mrs x9, {{pir_el1|PIR_EL1}} // encoding: [0x69,0xa2,0x38,0xd5]
// CHECK: mrs x9, {{pir_el12|PIR_EL12}} // encoding: [0x69,0xa2,0x3d,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 9b081974b40c7..90d94acba2ddd 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3421,6 +3421,7 @@
# CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12
# CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12
# CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12
+# CHECK: msr {{pire0_el12|PIRE0_EL12}}, x12
# CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12
# CHECK: msr {{pir_el1|PIR_EL1}}, x12
# CHECK: msr {{pir_el12|PIR_EL12}}, x12
@@ -3757,6 +3758,7 @@
# CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}}
# CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}}
# CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}}
+# CHECK: mrs x9, {{pire0_el12|PIRE0_EL12}}
# CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}}
# CHECK: mrs x9, {{pir_el1|PIR_EL1}}
# CHECK: mrs x9, {{pir_el12|PIR_EL12}}
@@ -4040,6 +4042,7 @@
0x2c 0xa1 0x1c 0xd5
0x2c 0xa1 0x1e 0xd5
0x4c 0xa2 0x18 0xd5
+0x4c 0xa2 0x1d 0xd5
0x4c 0xa2 0x1c 0xd5
0x6c 0xa2 0x18 0xd5
0x6c 0xa2 0x1d 0xd5
@@ -4378,6 +4381,7 @@
0x29 0xa1 0x3c 0xd5
0x29 0xa1 0x3e 0xd5
0x49 0xa2 0x38 0xd5
+0x49 0xa2 0x3d 0xd5
0x49 0xa2 0x3c 0xd5
0x69 0xa2 0x38 0xd5
0x69 0xa2 0x3d 0xd5
More information about the llvm-commits
mailing list