[PATCH] D142114: [AArch64][SME2] Add Multi-vector add/sub, storing into ZA intrinsic

[David Sherwood via Phabricator via llvm-commits]

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM! Before merging could you address the nits on the tests please? Thanks in advance. :)



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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -verify-machineinstrs < %s | FileCheck %s
+
----------------
nit: I don't think we need the `-mattr=+sve` here.


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -verify-machineinstrs < %s | FileCheck %s
+
----------------
nit: I don't think we need the `-mattr=+sve` here.


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll:8
+
+define void @multi_vector_sub_write_za_single_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,  <vscale x 4 x i32> %zm) {
+; CHECK-LABEL: multi_vector_sub_write_za_single_za_vg1x2_i32:
----------------
nit: 'za' appears twice in the test name - perhaps all the single tests in this file can just be named `@multi_vector_sub_write_single_za_vg1x2_i32`, etc?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D142114/new/

https://reviews.llvm.org/D142114