[PATCH] D141817: [NFC][AArch64] Append 'W' to LDAPUR.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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For load/store instructions, if the destination register has 32-bit and
64-bit forms, it will append 'W' and 'X' for the instructions. LDAPUR is
the only exception. There is LDAPURX for 64-bit form, but LDAPUR for
32-bit form. If there is no special reason, I think we should use the
same naming rule for LDAPUR.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141817

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp


Index: llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1270,7 +1270,7 @@
   case AArch64::LDAPURSBWi:
   case AArch64::LDAPURHi:
   case AArch64::LDAPURSHWi:
-  case AArch64::LDAPURi:
+  case AArch64::LDAPURWi:
     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURSBXi:
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3720,7 +3720,7 @@
 defm LDAPURH    : BaseLoadUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;
 defm LDAPURSHW  : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
 defm LDAPURSHX  : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
-defm LDAPUR     : BaseLoadUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
+defm LDAPURW    : BaseLoadUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
 defm LDAPURSW   : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
 defm LDAPURX    : BaseLoadUnscaleV84<"ldapur",   0b11, 0b01, GPR64>;
 }


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