[llvm] 4954c3c - [RISCV] Generate march string from target features
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llvm-commits at lists.llvm.org
Sun Jan 15 20:04:51 PST 2023
Author: wangpc
Date: 2023-01-16T12:03:59+08:00
New Revision: 4954c3c7b690c3cb484f6d18d3f3927aa65e21f4
URL: https://github.com/llvm/llvm-project/commit/4954c3c7b690c3cb484f6d18d3f3927aa65e21f4
DIFF: https://github.com/llvm/llvm-project/commit/4954c3c7b690c3cb484f6d18d3f3927aa65e21f4.diff
LOG: [RISCV] Generate march string from target features
As what has been mentioned in D137517, this patch is to simplify
processors definitions in RISCV.td. We don't have to specify march
string since we can generate it from target features.
Reviewed By: fpetrogalli, kito-cheng
Differential Revision: https://reviews.llvm.org/D141479
Added:
Modified:
llvm/lib/Target/RISCV/RISCV.td
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 5551a4a6497ca..750d03b604f76 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -576,8 +576,8 @@ include "RISCVSchedSyntacoreSCR1.td"
class RISCVProcessorModel<string n,
SchedMachineModel m,
list<SubtargetFeature> f,
- string default_march = "",
- list<SubtargetFeature> tunef = []>
+ list<SubtargetFeature> tunef = [],
+ string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
}
@@ -615,16 +615,14 @@ def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
RocketModel,
[Feature32Bit,
FeatureStdExtM,
- FeatureStdExtC],
- "rv32imc">;
+ FeatureStdExtC]>;
def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
RocketModel,
[Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC],
- "rv32imac">;
+ FeatureStdExtC]>;
def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
RocketModel,
@@ -632,16 +630,14 @@ def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC],
- "rv32imafc">;
+ FeatureStdExtC]>;
def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
RocketModel,
[Feature32Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC],
- "rv32imac">;
+ FeatureStdExtC]>;
def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
RocketModel,
@@ -649,8 +645,7 @@ def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
- FeatureStdExtC],
- "rv32imafc">;
+ FeatureStdExtC]>;
def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
SiFive7Model,
@@ -659,7 +654,6 @@ def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtC],
- "rv32imafc",
[TuneSiFive7]>;
def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
@@ -667,16 +661,14 @@ def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
[Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC],
- "rv64imac">;
+ FeatureStdExtC]>;
def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
RocketModel,
[Feature64Bit,
FeatureStdExtM,
FeatureStdExtA,
- FeatureStdExtC],
- "rv64imac">;
+ FeatureStdExtC]>;
def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
RocketModel,
@@ -685,8 +677,7 @@ def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC],
- "rv64gc">;
+ FeatureStdExtC]>;
def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
SiFive7Model,
@@ -696,7 +687,6 @@ def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- "rv64gc",
[TuneSiFive7]>;
def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
@@ -706,8 +696,7 @@ def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
- FeatureStdExtC],
- "rv64gc">;
+ FeatureStdExtC]>;
def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
SiFive7Model,
@@ -717,14 +706,12 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC],
- "rv64gc",
[TuneSiFive7] >;
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model,
[Feature32Bit,
FeatureStdExtC],
- "rv32ic",
[TuneNoDefaultUnroll]>;
def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
@@ -732,7 +719,6 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
[Feature32Bit,
FeatureStdExtM,
FeatureStdExtC],
- "rv32imc",
[TuneNoDefaultUnroll]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index cfd4a98a4be1c..db38ec89ceeb8 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -12,18 +12,50 @@
//===----------------------------------------------------------------------===//
#include "TableGenBackends.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/TableGen/Record.h"
using namespace llvm;
-static std::string getEnumFeatures(const Record &Rec) {
+using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
+
+static int getXLen(const Record &Rec) {
std::vector<Record *> Features = Rec.getValueAsListOfDefs("Features");
if (find_if(Features, [](const Record *R) {
return R->getName() == "Feature64Bit";
}) != Features.end())
- return "FK_64BIT";
+ return 64;
+
+ return 32;
+}
+
+// We can generate march string from target features as what has been described
+// in RISCV ISA specification (version 20191213) 'Chapter 27. ISA Extension
+// Naming Conventions'.
+//
+// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
+// get feature name from feature records instead of feature bits.
+static std::string getMArch(int XLen, const Record &Rec) {
+ std::vector<std::string> FeatureVector;
+
+ // Convert features to FeatureVector.
+ for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
+ StringRef FeatureName = Feature->getValueAsString("Name");
+ if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
+ FeatureVector.push_back((Twine("+") + FeatureName).str());
+ }
+
+ ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+ if (!ISAInfo)
+ report_fatal_error("Invalid features");
+
+ // RISCVISAInfo::toString will generate a march string with all the extensions
+ // we have added to it.
+ return (*ISAInfo)->toString();
+}
- return "FK_NONE";
+static std::string getEnumFeatures(int XLen) {
+ return XLen == 64 ? "FK_64BIT" : "FK_NONE";
}
void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
@@ -39,11 +71,19 @@ void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
// Iterate on all definition records.
for (const MapTy &Def : Map) {
const Record &Rec = *(Def.second);
- if (Rec.isSubClassOf("RISCVProcessorModel"))
+ if (Rec.isSubClassOf("RISCVProcessorModel")) {
+ int XLen = getXLen(Rec);
+ std::string MArch = Rec.getValueAsString("DefaultMarch").str();
+
+ // Compute MArch from features if we don't specify it.
+ if (MArch.empty())
+ MArch = getMArch(XLen, Rec);
+
OS << "PROC(" << Rec.getName() << ", "
<< "{\"" << Rec.getValueAsString("Name") << "\"},"
- << getEnumFeatures(Rec) << ", "
- << "{\"" << Rec.getValueAsString("DefaultMarch") << "\"})\n";
+ << getEnumFeatures(XLen) << ", "
+ << "{\"" << MArch << "\"})\n";
+ }
}
OS << "\n#undef PROC\n";
OS << "\n";
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