[PATCH] D141129: [InstCombine] Use KnownBits for lshr/add -> (a + b < a)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri requested changes to this revision.
lebedev.ri added a comment.
This revision now requires changes to proceed.

(marking as reviewed)



================
Comment at: llvm/test/Transforms/InstCombine/shift-add.ll:510
+
+define i32 @lshr_16_add_known_17_leading_zeroes(i32 %a, i32 %b) {
+; CHECK-LABEL: @lshr_16_add_known_17_leading_zeroes(
----------------
spatel wrote:
> Demanded bits should always zap cases like this.
> A more interesting test would have just one side of the add with extra leading zeros:
> https://alive2.llvm.org/ce/z/c4_YAE
> 
> So we'd be back to creating 2 extra instructions vs. the original sequence. That doesn't seem like a good trade-off in IR.
Presumably we can simply avoid that unprofitable case,
since e.g. `lshr_16_add_known_16_leading_zeroes()` looks like an improvement?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141129/new/

https://reviews.llvm.org/D141129