[PATCH] D127115: [RFC][DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added inline comments.


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Comment at: llvm/test/CodeGen/X86/bitreverse.ll:18
 ; X86-NEXT:    rolw $8, %ax
+; X86-NEXT:    movzwl %ax, %eax
 ; X86-NEXT:    movl %eax, %edx
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So this turns out to be cause by non topological processing, which is kind of ironic. We end up having `(and (srl (and 65535 x) 1) 21845)` which SimplifyDemandedBits should be able to take care of, except we already visited the outer and by the time we generate the inner and, so SimplifyDemandedBits never has a chance to do its job.

Is there a technique to sort this out? This is very similar to the problem @foad investigated.


Repository:
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  https://reviews.llvm.org/D127115/new/

https://reviews.llvm.org/D127115