[PATCH] D141074: [X86] Avoid converting 64-bit integers to floating point using x87 on Windows

[icedrocket via Phabricator via llvm-commits]

icedrocket updated this revision to Diff 489261.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141074/new/

https://reviews.llvm.org/D141074

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/uint64-to-float.ll


Index: llvm/test/CodeGen/X86/uint64-to-float.ll
===================================================================
--- llvm/test/CodeGen/X86/uint64-to-float.ll
+++ llvm/test/CodeGen/X86/uint64-to-float.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-apple-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-win32 -mattr=+sse2 | FileCheck %s --check-prefix=X86-WIN32
 
 ; Verify that we are using the efficient uitofp --> sitofp lowering illustrated
 ; by the compiler_rt implementation of __floatundisf.
@@ -42,6 +43,21 @@
 ; X64-NEXT:    cvtsi2ss %rdi, %xmm0
 ; X64-NEXT:    addss %xmm0, %xmm0
 ; X64-NEXT:    retq
+;
+; X86-WIN32-LABEL: test:
+; X86-WIN32:       # %bb.0: # %entry
+; X86-WIN32-NEXT:    pushl %ebp
+; X86-WIN32-NEXT:    movl %esp, %ebp
+; X86-WIN32-NEXT:    andl $-8, %esp
+; X86-WIN32-NEXT:    subl $8, %esp
+; X86-WIN32-NEXT:    pushl 12(%ebp)
+; X86-WIN32-NEXT:    pushl 8(%ebp)
+; X86-WIN32-NEXT:    calll ___floatundisf
+; X86-WIN32-NEXT:    addl $8, %esp
+; X86-WIN32-NEXT:    movl %ebp, %esp
+; X86-WIN32-NEXT:    popl %ebp
+; X86-WIN32-NEXT:    retl
+
 entry:
   %b = uitofp i64 %a to float
   ret float %b
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -21370,6 +21370,10 @@
   if (VT == MVT::f128 || !Subtarget.hasX87())
     return SDValue();
 
+  // On Windows, the default precision control on x87 is only 53-bit.
+  if (SrcVT == MVT::i64 && Subtarget.isOSWindows())
+    return SDValue();
+
   SDValue ValueToStore = Src;
   if (SrcVT == MVT::i64 && Subtarget.hasSSE2() && !Subtarget.is64Bit())
     // Bitcasting to f64 here allows us to do a single 64-bit store from
@@ -21882,6 +21886,11 @@
   }
 
   assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
+
+  // On Windows, the default precision control on x87 is only 53-bit.
+  if (Subtarget.isOSWindows())
+    return SDValue();
+
   SDValue ValueToStore = Src;
   if (isScalarFPTypeInSSEReg(Op.getValueType()) && !Subtarget.is64Bit()) {
     // Bitcasting to f64 here allows us to do a single 64-bit store from


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