[llvm] 79858d1 - [CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 13 23:13:09 PST 2023
Author: Craig Topper
Date: 2023-01-13T23:12:48-08:00
New Revision: 79858d1908b53560941b7d8f4d98e5ac781c674b
URL: https://github.com/llvm/llvm-project/commit/79858d1908b53560941b7d8f4d98e5ac781c674b
DIFF: https://github.com/llvm/llvm-project/commit/79858d1908b53560941b7d8f4d98e5ac781c674b.diff
LOG: [CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/include/llvm/CodeGen/LiveRegUnits.h
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/include/llvm/CodeGen/Register.h
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallLowering.cpp
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/lib/Target/ARM/ARMScheduleA9.td
llvm/lib/Target/ARM/MLxExpansionPass.cpp
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/lib/Target/BPF/BPFMIPeephole.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
llvm/lib/Target/X86/X86DomainReassignment.cpp
llvm/lib/Target/X86/X86ExpandPseudo.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86OptimizeLEAs.cpp
llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
index baa996a5bcdb..fc4e94929d41 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
@@ -118,7 +118,7 @@ bool InstructionSelector::executeMatchTable(
return false;
break;
}
- if (Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.getReg().isPhysical()) {
DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
dbgs() << CurrentIdx << ": Is a physical register\n");
if (handleReject() == RejectAndGiveUp)
diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h
index 39a1ec461ef6..a5a8fc6d92a3 100644
--- a/llvm/include/llvm/CodeGen/LiveRegUnits.h
+++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h
@@ -166,8 +166,8 @@ inline iterator_range<filter_iterator<
phys_regs_and_masks(const MachineInstr &MI) {
std::function<bool(const MachineOperand &)> Pred =
[](const MachineOperand &MOP) {
- return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() &&
- Register::isPhysicalRegister(MOP.getReg()));
+ return MOP.isRegMask() ||
+ (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical());
};
return make_filter_range(const_mi_bundle_ops(MI), Pred);
}
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index 04cb331e5d04..c35bdc0c2b44 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -555,7 +555,7 @@ inline unsigned getRegState(const MachineOperand &RegOp) {
getUndefRegState(RegOp.isUndef()) |
getInternalReadRegState(RegOp.isInternalRead()) |
getDebugRegState(RegOp.isDebug()) |
- getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) &&
+ getRenamableRegState(RegOp.getReg().isPhysical() &&
RegOp.isRenamable());
}
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 572217213920..7f0c24e4e115 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -757,7 +757,7 @@ class MachineRegisterInfo {
/// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
/// (target independent) virtual register.
LLT getType(Register Reg) const {
- if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
+ if (Reg.isVirtual() && VRegToType.inBounds(Reg))
return VRegToType[Reg];
return LLT{};
}
@@ -799,7 +799,7 @@ class MachineRegisterInfo {
/// addRegAllocationHint - Add a register allocation hint to the hints
/// vector for VReg.
void addRegAllocationHint(Register VReg, Register PrefReg) {
- assert(Register::isVirtualRegister(VReg));
+ assert(VReg.isVirtual());
RegAllocHints[VReg].second.push_back(PrefReg);
}
diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h
index 9dc3e98fe837..2f2d58f5185b 100644
--- a/llvm/include/llvm/CodeGen/Register.h
+++ b/llvm/include/llvm/CodeGen/Register.h
@@ -75,7 +75,7 @@ class Register {
/// Convert a virtual register number to a 0-based index.
/// The first virtual register in a function will get the index 0.
static unsigned virtReg2Index(Register Reg) {
- assert(isVirtualRegister(Reg) && "Not a virtual register");
+ assert(Reg.isVirtual() && "Not a virtual register");
return Reg & ~MCRegister::VirtualRegFlag;
}
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 1aee0a851f1b..b8b6ddc33f66 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -733,7 +733,7 @@ void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
llvm_unreachable("<unknown operand type>");
case MachineOperand::MO_Register: {
Register Reg = MO.getReg();
- assert(Register::isPhysicalRegister(Reg));
+ assert(Reg.isPhysical());
assert(!MO.getSubReg() && "Subregs should be eliminated!");
O << AArch64InstPrinter::getRegisterName(Reg);
break;
diff --git a/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp b/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
index d65929eff12f..da72e35a248e 100644
--- a/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
@@ -79,7 +79,7 @@ void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {
}
MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
- if (!Register::isVirtualRegister(MO.getReg()))
+ if (!MO.getReg().isVirtual())
return nullptr;
return MRI->getUniqueVRegDef(MO.getReg());
}
diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
index bc3808df1dbc..3e04cbae8acf 100644
--- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
@@ -146,8 +146,7 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
// We should not have any relevant physreg defs that are replacable by
// zero before register allocation. So we just check for dead vreg defs.
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg) ||
- (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
+ if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
continue;
assert(!MO.isImplicit() && "Unexpected implicit def!");
LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a81079943a7d..4211ab390395 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1199,7 +1199,7 @@ static bool UpdateOperandRegClass(MachineInstr &Instr) {
"Operand has register constraints without being a register!");
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (!OpRegCstraints->contains(Reg))
return false;
} else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
@@ -3803,7 +3803,7 @@ static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI,
MachineMemOperand *MMO) {
Register SrcReg0 = SrcReg;
Register SrcReg1 = SrcReg;
- if (Register::isPhysicalRegister(SrcReg)) {
+ if (SrcReg.isPhysical()) {
SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0);
SubIdx0 = 0;
SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1);
@@ -3850,7 +3850,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::STRWui;
- if (Register::isVirtualRegister(SrcReg))
+ if (SrcReg.isVirtual())
MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
else
assert(SrcReg != AArch64::WSP);
@@ -3860,7 +3860,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
case 8:
if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::STRXui;
- if (Register::isVirtualRegister(SrcReg))
+ if (SrcReg.isVirtual())
MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
else
assert(SrcReg != AArch64::SP);
@@ -3958,7 +3958,7 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
Register DestReg0 = DestReg;
Register DestReg1 = DestReg;
bool IsUndef = true;
- if (Register::isPhysicalRegister(DestReg)) {
+ if (DestReg.isPhysical()) {
DestReg0 = TRI.getSubReg(DestReg, SubIdx0);
SubIdx0 = 0;
DestReg1 = TRI.getSubReg(DestReg, SubIdx1);
@@ -4006,7 +4006,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::LDRWui;
- if (Register::isVirtualRegister(DestReg))
+ if (DestReg.isVirtual())
MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
else
assert(DestReg != AArch64::WSP);
@@ -4016,7 +4016,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
case 8:
if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::LDRXui;
- if (Register::isVirtualRegister(DestReg))
+ if (DestReg.isVirtual())
MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
else
assert(DestReg != AArch64::SP);
@@ -4481,11 +4481,11 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
if (MI.isFullCopy()) {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
- if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
+ if (SrcReg == AArch64::SP && DstReg.isVirtual()) {
MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
return nullptr;
}
- if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
+ if (DstReg == AArch64::SP && SrcReg.isVirtual()) {
MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
return nullptr;
}
@@ -4559,7 +4559,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
//
// STRXui %xzr, %stack.0
//
- if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
+ if (IsSpill && DstMO.isUndef() && SrcReg.isPhysical()) {
assert(SrcMO.getSubReg() == 0 &&
"Unexpected subreg on physical register");
const TargetRegisterClass *SpillRC;
@@ -4901,7 +4901,7 @@ static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineInstr *MI = nullptr;
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.getReg().isVirtual())
MI = MRI.getUniqueVRegDef(MO.getReg());
// And it needs to be in the trace (otherwise, it won't have a depth).
if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc)
@@ -5343,7 +5343,7 @@ static bool getFMULPatterns(MachineInstr &Root,
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineOperand &MO = Root.getOperand(Operand);
MachineInstr *MI = nullptr;
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.getReg().isVirtual())
MI = MRI.getUniqueVRegDef(MO.getReg());
// Ignore No-op COPYs in FMUL(COPY(DUP(..)))
if (MI && MI->getOpcode() == TargetOpcode::COPY &&
@@ -5601,7 +5601,7 @@ genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI,
Register SrcReg1 = MUL->getOperand(2).getReg();
bool Src1IsKill = MUL->getOperand(2).isKill();
- unsigned SrcReg2;
+ Register SrcReg2;
bool Src2IsKill;
if (ReplacedAddend) {
// If we just generated a new addend, we must be it's only use.
@@ -5612,13 +5612,13 @@ genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI,
Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
}
- if (Register::isVirtualRegister(ResultReg))
+ if (ResultReg.isVirtual())
MRI.constrainRegClass(ResultReg, RC);
- if (Register::isVirtualRegister(SrcReg0))
+ if (SrcReg0.isVirtual())
MRI.constrainRegClass(SrcReg0, RC);
- if (Register::isVirtualRegister(SrcReg1))
+ if (SrcReg1.isVirtual())
MRI.constrainRegClass(SrcReg1, RC);
- if (Register::isVirtualRegister(SrcReg2))
+ if (SrcReg2.isVirtual())
MRI.constrainRegClass(SrcReg2, RC);
MachineInstrBuilder MIB;
@@ -5791,11 +5791,11 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
Register SrcReg1 = MUL->getOperand(2).getReg();
bool Src1IsKill = MUL->getOperand(2).isKill();
- if (Register::isVirtualRegister(ResultReg))
+ if (ResultReg.isVirtual())
MRI.constrainRegClass(ResultReg, RC);
- if (Register::isVirtualRegister(SrcReg0))
+ if (SrcReg0.isVirtual())
MRI.constrainRegClass(SrcReg0, RC);
- if (Register::isVirtualRegister(SrcReg1))
+ if (SrcReg1.isVirtual())
MRI.constrainRegClass(SrcReg1, RC);
if (Register::isVirtualRegister(VR))
MRI.constrainRegClass(VR, RC);
@@ -6871,7 +6871,7 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo *MRI = &MF->getRegInfo();
Register VReg = MI.getOperand(0).getReg();
- if (!Register::isVirtualRegister(VReg))
+ if (!VReg.isVirtual())
return false;
MachineInstr *DefMI = MRI->getVRegDef(VReg);
@@ -6907,7 +6907,7 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
MachineOperand &MO = DefMI->getOperand(1);
Register NewReg = MO.getReg();
- if (!Register::isVirtualRegister(NewReg))
+ if (!NewReg.isVirtual())
return false;
assert(!MRI->def_empty(NewReg) && "Register must be defined.");
diff --git a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
index b7700baf79fc..2cbac9783bbd 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
@@ -185,8 +185,7 @@ void AArch64StackTaggingPreRA::uncheckUsesOf(unsigned TaggedReg, int FI) {
UseI.getOperand(OpIdx).ChangeToFrameIndex(FI);
UseI.getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
}
- } else if (UseI.isCopy() &&
- Register::isVirtualRegister(UseI.getOperand(0).getReg())) {
+ } else if (UseI.isCopy() && UseI.getOperand(0).getReg().isVirtual()) {
uncheckUsesOf(UseI.getOperand(0).getReg(), FI);
}
}
@@ -266,7 +265,7 @@ std::optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
continue;
Register RetagReg = I->getOperand(0).getReg();
- if (!Register::isVirtualRegister(RetagReg))
+ if (!RetagReg.isVirtual())
continue;
int Score = 0;
@@ -285,7 +284,7 @@ std::optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
continue;
if (UseI.isCopy()) {
Register DstReg = UseI.getOperand(0).getReg();
- if (Register::isVirtualRegister(DstReg))
+ if (DstReg.isVirtual())
WorkList.push_back(DstReg);
continue;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 4badb81a9b48..0c1c6e14b02b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -723,7 +723,7 @@ static bool unsupportedBinOp(const MachineInstr &I,
// so, this will need to be taught about that, and we'll need to get the
// bank out of the minimal class for the register.
// Either way, this needs to be documented (and possibly verified).
- if (!Register::isVirtualRegister(MO.getReg())) {
+ if (!MO.getReg().isVirtual()) {
LLVM_DEBUG(dbgs() << "Generic inst has physical register operand\n");
return true;
}
@@ -871,7 +871,7 @@ static bool copySubReg(MachineInstr &I, MachineRegisterInfo &MRI,
// It's possible that the destination register won't be constrained. Make
// sure that happens.
- if (!Register::isPhysicalRegister(I.getOperand(0).getReg()))
+ if (!I.getOperand(0).getReg().isPhysical())
RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
return true;
@@ -1006,7 +1006,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
// If the destination is a physical register, then there's nothing to
// change, so we're done.
- if (Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
return true;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 0006abdbde5f..d6d5c6047747 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -629,10 +629,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
// Check if one of the register is not a generic register.
- if ((Register::isPhysicalRegister(DstReg) ||
- !MRI.getType(DstReg).isValid()) ||
- (Register::isPhysicalRegister(SrcReg) ||
- !MRI.getType(SrcReg).isValid())) {
+ if ((DstReg.isPhysical() || !MRI.getType(DstReg).isValid()) ||
+ (SrcReg.isPhysical() || !MRI.getType(SrcReg).isValid())) {
const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
if (!DstRB)
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index d200ad6df6fb..6d901d6783f0 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -329,7 +329,7 @@ void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock,
// Do not Track Physical Registers, because it messes up.
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
- if (Register::isVirtualRegister(RegMaskPair.RegUnit))
+ if (RegMaskPair.RegUnit.isVirtual())
LiveInRegs.insert(RegMaskPair.RegUnit);
}
LiveOutRegs.clear();
diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
index 9bced0661dff..3543cefeb399 100644
--- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp
+++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
@@ -135,7 +135,7 @@ bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
return false;
Register Reg = MO.getReg();
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
else
return TRC->contains(Reg);
@@ -190,7 +190,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
if ((!MO.isReg()) || (!MO.isUse()))
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
MachineOperand *Op = MI->findRegisterDefOperand(Reg);
@@ -212,7 +212,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
if ((!MODef.isReg()) || (!MODef.isDef()))
continue;
Register DefReg = MODef.getReg();
- if (!Register::isVirtualRegister(DefReg)) {
+ if (!DefReg.isVirtual()) {
IsDead = false;
break;
}
@@ -246,7 +246,7 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
Register DPRReg = MI->getOperand(1).getReg();
Register SPRReg = MI->getOperand(2).getReg();
- if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
+ if (DPRReg.isVirtual() && SPRReg.isVirtual()) {
MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
@@ -296,7 +296,7 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
++NumTotal;
Register OpReg = MO.getReg();
- if (!Register::isVirtualRegister(OpReg))
+ if (!OpReg.isVirtual())
break;
MachineInstr *Def = MRI->getVRegDef(OpReg);
@@ -340,7 +340,7 @@ bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
if (!MI->isFullCopy())
return MI;
- if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
+ if (!MI->getOperand(1).getReg().isVirtual())
return nullptr;
MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
if (!Def)
@@ -366,7 +366,7 @@ void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
if (MI->isPHI()) {
for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
Register Reg = MI->getOperand(I).getReg();
- if (!Register::isVirtualRegister(Reg)) {
+ if (!Reg.isVirtual()) {
continue;
}
MachineInstr *NewMI = MRI->getVRegDef(Reg);
@@ -375,7 +375,7 @@ void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
Front.push_back(NewMI);
}
} else if (MI->isFullCopy()) {
- if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
+ if (!MI->getOperand(1).getReg().isVirtual())
continue;
MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
if (!NewMI)
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index bcd3ea2153b7..5c0c3b30d96e 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -212,7 +212,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
default: llvm_unreachable("<unknown operand type>");
case MachineOperand::MO_Register: {
Register Reg = MO.getReg();
- assert(Register::isPhysicalRegister(Reg));
+ assert(Reg.isPhysical());
assert(!MO.getSubReg() && "Subregs should be eliminated!");
if(ARM::GPRPairRegClass.contains(Reg)) {
const MachineFunction &MF = *MI->getParent()->getParent();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 992b6f396be5..0b345085a99f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -313,7 +313,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
// Transfer LiveVariables states, kill / dead info.
if (LV) {
for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
+ if (MO.isReg() && MO.getReg().isVirtual()) {
Register Reg = MO.getReg();
LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
@@ -1443,7 +1443,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
}
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
} else
llvm_unreachable("Unknown reg class!");
@@ -1489,7 +1489,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
}
} else
@@ -1519,7 +1519,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
}
} else
@@ -1544,7 +1544,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
} else
llvm_unreachable("Unknown reg class!");
@@ -1910,8 +1910,7 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
Register Addr0 = MI0.getOperand(1).getReg();
Register Addr1 = MI1.getOperand(1).getReg();
if (Addr0 != Addr1) {
- if (!MRI || !Register::isVirtualRegister(Addr0) ||
- !Register::isVirtualRegister(Addr1))
+ if (!MRI || !Addr0.isVirtual() || !Addr1.isVirtual())
return false;
// This assumes SSA form.
@@ -2318,7 +2317,7 @@ ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
// MI can't have any tied operands, that would conflict with predication.
if (MO.isTied())
return nullptr;
- if (Register::isPhysicalRegister(MO.getReg()))
+ if (MO.getReg().isPhysical())
return nullptr;
if (MO.isDef() && !MO.isDead())
return nullptr;
@@ -5380,7 +5379,7 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
return 0;
// We must be able to clobber the whole D-reg.
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
// Virtual register must be a def undef foo:ssub_0 operand.
if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
return 0;
@@ -5406,8 +5405,7 @@ void ARMBaseInstrInfo::breakPartialRegDependency(
const MachineOperand &MO = MI.getOperand(OpNum);
Register Reg = MO.getReg();
- assert(Register::isPhysicalRegister(Reg) &&
- "Can't break virtual register dependencies.");
+ assert(Reg.isPhysical() && "Can't break virtual register dependencies.");
unsigned DReg = Reg;
// If MI defines an S-reg, find the corresponding D super-register.
@@ -6887,14 +6885,14 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
for (auto &S : SU.Succs)
if (MI->isPHI() && S.getKind() == SDep::Anti) {
Register Reg = S.getReg();
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed()))
.first->second.set(0);
} else if (S.isAssignedRegDep()) {
int OStg = SMS.stageScheduled(S.getSUnit());
if (OStg >= 0 && OStg != Stg) {
Register Reg = S.getReg();
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed()))
.first->second |= ((1 << (OStg - Stg)) - 1);
}
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index cf156f4c92ea..e6c6ab2efd50 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -403,7 +403,7 @@ void ARMBaseRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
// Make sure the pair has not already divorced.
if (Hint.second == Reg) {
MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
- if (Register::isVirtualRegister(NewReg))
+ if (NewReg.isVirtual())
MRI->setRegAllocationHint(NewReg,
Hint.first == ARMRI::RegPairOdd
? ARMRI::RegPairEven
@@ -855,8 +855,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
const TargetRegisterClass *RegClass =
TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());
- if (Offset == 0 &&
- (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
+ if (Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)))
// Must be addrmode4/6.
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
else {
diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp
index 1d204a44ddfb..76b99403a2f8 100644
--- a/llvm/lib/Target/ARM/ARMCallLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp
@@ -480,7 +480,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &
MIB.add(Info.Callee);
if (!IsDirect) {
auto CalleeReg = Info.Callee.getReg();
- if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
+ if (CalleeReg && !CalleeReg.isPhysical()) {
unsigned CalleeIdx = IsThumb ? 2 : 0;
MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 960adc80d71a..7edd58e0ae56 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1220,7 +1220,7 @@ ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
Register Reg = Op.getReg();
if (Reg == ARM::NoRegister || Reg == ARM::LR)
continue;
- assert(Register::isPhysicalRegister(Reg) && "Unallocated register");
+ assert(Reg.isPhysical() && "Unallocated register");
ClearBB->addLiveIn(Reg);
DoneBB->addLiveIn(Reg);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 6acd6fb3f5e5..dd68153f1418 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2938,7 +2938,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
int FI = std::numeric_limits<int>::max();
if (Arg.getOpcode() == ISD::CopyFromReg) {
Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
- if (!Register::isVirtualRegister(VR))
+ if (!VR.isVirtual())
return false;
MachineInstr *Def = MRI->getVRegDef(VR);
if (!Def)
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 624db8838dcf..a4ab2f86d046 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -212,7 +212,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
Register DstReg = I.getOperand(0).getReg();
- if (Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
return true;
const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td
index be7017a7b426..8b375d3602c2 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA9.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA9.td
@@ -2239,9 +2239,9 @@ def A9WriteLMfpPostRA : SchedWriteVariant<[
// Distinguish between our multiple MI-level forms of the same
// VLDM/VSTM instructions.
def A9PreRA : SchedPredicate<
- "Register::isVirtualRegister(MI->getOperand(0).getReg())">;
+ "MI->getOperand(0).getReg().isVirtual()">;
def A9PostRA : SchedPredicate<
- "Register::isPhysicalRegister(MI->getOperand(0).getReg())">;
+ "MI->getOperand(0).getReg().isPhysical()">;
// VLDM represents all destination registers as a single register
// tuple, unlike LDM. So the number of write operands is not variadic.
diff --git a/llvm/lib/Target/ARM/MLxExpansionPass.cpp b/llvm/lib/Target/ARM/MLxExpansionPass.cpp
index cc31929899b4..00d8d84654de 100644
--- a/llvm/lib/Target/ARM/MLxExpansionPass.cpp
+++ b/llvm/lib/Target/ARM/MLxExpansionPass.cpp
@@ -87,7 +87,7 @@ MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const {
// Look past COPY and INSERT_SUBREG instructions to find the
// real definition MI. This is important for _sfp instructions.
Register Reg = MI->getOperand(1).getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
return nullptr;
MachineBasicBlock *MBB = MI->getParent();
@@ -97,13 +97,13 @@ MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const {
break;
if (DefMI->isCopyLike()) {
Reg = DefMI->getOperand(1).getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
DefMI = MRI->getVRegDef(Reg);
continue;
}
} else if (DefMI->isInsertSubreg()) {
Reg = DefMI->getOperand(2).getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
DefMI = MRI->getVRegDef(Reg);
continue;
}
@@ -115,7 +115,7 @@ MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const {
unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
Register Reg = MI->getOperand(0).getReg();
- if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg))
+ if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg))
return Reg;
MachineBasicBlock *MBB = MI->getParent();
@@ -125,7 +125,7 @@ unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
Reg = UseMI->getOperand(0).getReg();
- if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg))
+ if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg))
return Reg;
UseMI = &*MRI->use_instr_nodbg_begin(Reg);
if (UseMI->getParent() != MBB)
@@ -139,7 +139,7 @@ unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
/// a single-MBB loop.
bool MLxExpansion::hasLoopHazard(MachineInstr *MI) const {
Register Reg = MI->getOperand(1).getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
return false;
MachineBasicBlock *MBB = MI->getParent();
@@ -153,7 +153,7 @@ bool MLxExpansion::hasLoopHazard(MachineInstr *MI) const {
for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) {
if (DefMI->getOperand(i + 1).getMBB() == MBB) {
Register SrcReg = DefMI->getOperand(i).getReg();
- if (Register::isVirtualRegister(SrcReg)) {
+ if (SrcReg.isVirtual()) {
DefMI = MRI->getVRegDef(SrcReg);
goto outer_continue;
}
@@ -161,13 +161,13 @@ bool MLxExpansion::hasLoopHazard(MachineInstr *MI) const {
}
} else if (DefMI->isCopyLike()) {
Reg = DefMI->getOperand(1).getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
DefMI = MRI->getVRegDef(Reg);
continue;
}
} else if (DefMI->isInsertSubreg()) {
Reg = DefMI->getOperand(2).getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
DefMI = MRI->getVRegDef(Reg);
continue;
}
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index f077435a2cc7..48eaa80ebc65 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -82,11 +82,11 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI,
Register VReg) const {
assert((RC == &ARM::tGPRRegClass ||
- (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) &&
+ (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
"Unknown regclass!");
if (RC == &ARM::tGPRRegClass ||
- (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) {
+ (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
@@ -110,13 +110,12 @@ void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
Register VReg) const {
- assert(
- (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
- (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) &&
- "Unknown regclass!");
+ assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
+ (DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
+ "Unknown regclass!");
if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
- (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) {
+ (DestReg.isPhysical() && isARMLowRegister(DestReg))) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index b5ebd08f3370..d06f182b0d0e 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -189,7 +189,7 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
// Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
// otherwise).
- if (Register::isVirtualRegister(SrcReg)) {
+ if (SrcReg.isVirtual()) {
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
}
@@ -232,7 +232,7 @@ void Thumb2InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
// Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
// otherwise).
- if (Register::isVirtualRegister(DestReg)) {
+ if (DestReg.isVirtual()) {
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
}
@@ -242,7 +242,7 @@ void Thumb2InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
MIB.addReg(DestReg, RegState::ImplicitDefine);
return;
}
@@ -722,9 +722,8 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
int ImmedOffset = Offset / Scale;
unsigned Mask = (1 << NumBits) - 1;
if ((unsigned)Offset <= Mask * Scale &&
- (Register::isVirtualRegister(FrameReg) ||
- RegClass->contains(FrameReg))) {
- if (Register::isVirtualRegister(FrameReg)) {
+ (FrameReg.isVirtual() || RegClass->contains(FrameReg))) {
+ if (FrameReg.isVirtual()) {
// Make sure the register class for the virtual register is correct
MachineRegisterInfo *MRI = &MF.getRegInfo();
if (!MRI->constrainRegClass(FrameReg, RegClass))
@@ -763,8 +762,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
}
Offset = (isSub) ? -Offset : Offset;
- return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
- RegClass->contains(FrameReg));
+ return Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg));
}
ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index ef24cc9d5b86..a29095e6b81a 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -141,7 +141,7 @@ static void emitThumbRegPlusImmInReg(
Register LdReg = DestReg;
if (DestReg == ARM::SP)
assert(BaseReg == ARM::SP && "Unexpected!");
- if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg))
+ if (!isARMLowRegister(DestReg) && !DestReg.isVirtual())
LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp
index cefbe48b7217..d0272bd97bed 100644
--- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp
+++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp
@@ -99,7 +99,7 @@ bool BPFMIPeephole::isCopyFrom32Def(MachineInstr *CopyMI)
// Most likely, this physical register is aliased to
// function call return value or current function parameters.
Register Reg = opnd.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return false;
if (MRI->getRegClass(Reg) == &BPF::GPRRegClass)
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 6e661ad4a63e..aab543dde76b 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -1223,7 +1223,7 @@ bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
RegisterRef RD = MI.getOperand(0);
RegisterRef RS = MI.getOperand(1);
assert(RD.Sub == 0);
- if (!Register::isPhysicalRegister(RS.Reg))
+ if (!RS.Reg.isPhysical())
return false;
RegExtMap::const_iterator F = VRX.find(RD.Reg);
if (F == VRX.end())
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index dbb22875939e..38103cdd30ad 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -268,7 +268,7 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs(
return SRs;
}
- if (Register::isPhysicalRegister(R.Reg)) {
+ if (R.Reg.isPhysical()) {
MCSubRegIterator I(R.Reg, &TRI);
if (!I.isValid())
SRs.insert({R.Reg, 0});
@@ -321,7 +321,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
if (!Op.isReg() || !Op.isUse() || Op.isUndef())
continue;
RegisterRef R = { Op.getReg(), Op.getSubReg() };
- if (Register::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
+ if (R.Reg.isPhysical() && Reserved[R.Reg])
continue;
bool IsKill = Op.isKill();
for (auto S : expandToSubRegs(R, MRI, TRI)) {
@@ -338,7 +338,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
continue;
RegisterRef R = { Op.getReg(), Op.getSubReg() };
for (auto S : expandToSubRegs(R, MRI, TRI)) {
- if (Register::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
+ if (S.Reg.isPhysical() && Reserved[S.Reg])
continue;
if (Op.isDead())
Clobbers.insert(S);
@@ -374,7 +374,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
// Update maps for defs.
for (RegisterRef S : Defs) {
// Defs should already be expanded into subregs.
- assert(!Register::isPhysicalRegister(S.Reg) ||
+ assert(!S.Reg.isPhysical() ||
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
@@ -383,7 +383,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
// Update maps for clobbers.
for (RegisterRef S : Clobbers) {
// Clobbers should already be expanded into subregs.
- assert(!Register::isPhysicalRegister(S.Reg) ||
+ assert(!S.Reg.isPhysical() ||
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index d39801fb4546..a636f7c4264e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2219,12 +2219,12 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
if (RegA == RegB)
return true;
- if (Register::isPhysicalRegister(RegA))
+ if (RegA.isPhysical())
for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
if (RegB == *SubRegs)
return true;
- if (Register::isPhysicalRegister(RegB))
+ if (RegB.isPhysical())
for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
if (RegA == *SubRegs)
return true;
@@ -4302,7 +4302,7 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
// Get DefIdx and UseIdx for super registers.
const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
- if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
+ if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
if (DefMO.isImplicit()) {
for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 0b05b35a5a60..8917be1b5626 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -351,8 +351,7 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
// The code below checks for all the physical registers, not just R0/D0/V0.
else if (SchedRetvalOptimization) {
const MachineInstr *MI = DAG->SUnits[su].getInstr();
- if (MI->isCopy() &&
- Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
+ if (MI->isCopy() && MI->getOperand(1).getReg().isPhysical()) {
// %vregX = COPY %r0
VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
LastVRegUse.erase(MI->getOperand(1).getReg());
@@ -364,7 +363,7 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
VRegHoldingReg.count(MO.getReg())) {
// <use of %vregX>
LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
- } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
+ } else if (MO.isDef() && MO.getReg().isPhysical()) {
for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
++AI) {
if (LastVRegUse.count(*AI) &&
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index b78fb380f982..42b088a6fd00 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -476,7 +476,7 @@ static MachineInstr *canFoldIntoSelect(Register Reg,
// MI can't have any tied operands, that would conflict with predication.
if (MO.isTied())
return nullptr;
- if (Register::isPhysicalRegister(MO.getReg()))
+ if (MO.getReg().isPhysical())
return nullptr;
if (MO.isDef() && !MO.isDead())
return nullptr;
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index 8bc319752e7d..bb527dca6b6d 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -354,7 +354,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
MachineOperand &MO = II->getOperand(i);
if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
- !Register::isVirtualRegister(MO.getReg()))
+ !MO.getReg().isVirtual())
Candidates.reset(MO.getReg());
}
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 59f158688b16..04fe0960998d 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -105,7 +105,7 @@ bool MipsInstructionSelector::isRegInFprb(Register Reg,
bool MipsInstructionSelector::selectCopy(MachineInstr &I,
MachineRegisterInfo &MRI) const {
Register DstReg = I.getOperand(0).getReg();
- if (Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
return true;
const TargetRegisterClass *RC = getRegClassForTypeOnBank(DstReg, MRI);
@@ -427,7 +427,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
const Register DestReg = I.getOperand(0).getReg();
const TargetRegisterClass *DefRC = nullptr;
- if (Register::isPhysicalRegister(DestReg))
+ if (DestReg.isPhysical())
DefRC = TRI.getRegClass(DestReg);
else
DefRC = getRegClassForTypeOnBank(DestReg, MRI);
diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
index 204c42ae5e5f..96fd9abfa19f 100644
--- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -127,7 +127,7 @@ static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) {
MachineOperand &MO = MI.getOperand(0);
- if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.isUse() || !MO.getReg().isVirtual())
return nullptr;
return &MO;
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 2544d9d9b76d..b4f4f3007c69 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -184,7 +184,7 @@ void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
MachineInstr *NonCopyInstr = skipCopiesOutgoing(&UseMI);
// Copy with many uses.
if (NonCopyInstr->getOpcode() == TargetOpcode::COPY &&
- !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg()))
+ !NonCopyInstr->getOperand(0).getReg().isPhysical())
addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI);
else
DefUses.push_back(skipCopiesOutgoing(&UseMI));
@@ -206,7 +206,7 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(
const MachineRegisterInfo &MRI = MF.getRegInfo();
MachineInstr *Ret = MI;
while (Ret->getOpcode() == TargetOpcode::COPY &&
- !Register::isPhysicalRegister(Ret->getOperand(0).getReg()) &&
+ !Ret->getOperand(0).getReg().isPhysical() &&
MRI.hasOneUse(Ret->getOperand(0).getReg())) {
Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg()));
}
@@ -220,7 +220,7 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(
const MachineRegisterInfo &MRI = MF.getRegInfo();
MachineInstr *Ret = MI;
while (Ret->getOpcode() == TargetOpcode::COPY &&
- !Register::isPhysicalRegister(Ret->getOperand(1).getReg()))
+ !Ret->getOperand(1).getReg().isPhysical())
Ret = MRI.getVRegDef(Ret->getOperand(1).getReg());
return Ret;
}
@@ -360,7 +360,7 @@ void MipsRegisterBankInfo::TypeInfoForMF::setTypes(const MachineInstr *MI,
void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(
const MachineInstr *MI, const MachineInstr *CopyInst, unsigned Op) {
- assert((Register::isPhysicalRegister(CopyInst->getOperand(Op).getReg())) &&
+ assert((CopyInst->getOperand(Op).getReg().isPhysical()) &&
"Copies of non physical registers should not be considered here.\n");
const MachineFunction &MF = *CopyInst->getMF();
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index 83786281a05c..9acad670aa7e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -515,7 +515,7 @@ const MCSymbol *NVPTXAsmPrinter::getFunctionFrameSymbol() const {
void NVPTXAsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
Register RegNo = MI->getOperand(0).getReg();
- if (Register::isVirtualRegister(RegNo)) {
+ if (RegNo.isVirtual()) {
OutStreamer->AddComment(Twine("implicit-def: ") +
getVirtualRegisterName(RegNo));
} else {
@@ -2175,7 +2175,7 @@ void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.getReg().isPhysical()) {
if (MO.getReg() == NVPTX::VRDepot)
O << DEPOTNAME << getFunctionNumber();
else
diff --git a/llvm/lib/Target/NVPTX/NVPTXPeephole.cpp b/llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
index bf3c87df2e08..0968701737e8 100644
--- a/llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
@@ -83,7 +83,7 @@ static bool isCVTAToLocalCombinationCandidate(MachineInstr &Root) {
auto &Op = Root.getOperand(1);
const auto &MRI = MF.getRegInfo();
MachineInstr *GenericAddrDef = nullptr;
- if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
+ if (Op.isReg() && Op.getReg().isVirtual()) {
GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
}
diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
index 786a3e163540..9d580ff57471 100644
--- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
@@ -346,8 +346,7 @@ bool PPCBranchCoalescing::identicalOperands(
if (Op1.isIdenticalTo(Op2)) {
// filter out instructions with physical-register uses
- if (Op1.isReg() &&
- Register::isPhysicalRegister(Op1.getReg())
+ if (Op1.isReg() && Op1.getReg().isPhysical()
// If the physical register is constant then we can assume the value
// has not changed between uses.
&& !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) {
@@ -361,9 +360,8 @@ bool PPCBranchCoalescing::identicalOperands(
// If the operands are not identical, but are registers, check to see if the
// definition of the register produces the same value. If they produce the
// same value, consider them to be identical.
- if (Op1.isReg() && Op2.isReg() &&
- Register::isVirtualRegister(Op1.getReg()) &&
- Register::isVirtualRegister(Op2.getReg())) {
+ if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() &&
+ Op2.getReg().isVirtual()) {
MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg());
MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
if (TII->produceSameValue(*Op1Def, *Op2Def, MRI)) {
@@ -463,7 +461,7 @@ bool PPCBranchCoalescing::canMoveToEnd(const MachineInstr &MI,
<< TargetMBB.getNumber() << "\n");
for (auto &Use : MI.uses()) {
- if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
+ if (Use.isReg() && Use.getReg().isVirtual()) {
MachineInstr *DefInst = MRI->getVRegDef(Use.getReg());
if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) {
LLVM_DEBUG(dbgs() << " *** Cannot move this instruction ***\n");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cb93d2a8f999..356f102085e2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11721,8 +11721,8 @@ MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
MachineFunction *F = BB->getParent();
MachineRegisterInfo &RegInfo = F->getRegInfo();
Register incr = MI.getOperand(3).getReg();
- bool IsSignExtended = Register::isVirtualRegister(incr) &&
- isSignExtended(*RegInfo.getVRegDef(incr), TII);
+ bool IsSignExtended =
+ incr.isVirtual() && isSignExtended(*RegInfo.getVRegDef(incr), TII);
if (CmpOpcode == PPC::CMPW && !IsSignExtended) {
Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index b30f8addcf84..77b507d113f8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -179,7 +179,7 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
Register Reg = DefMO.getReg();
bool IsRegCR;
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
const MachineRegisterInfo *MRI =
&DefMI.getParent()->getParent()->getRegInfo();
IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
@@ -378,7 +378,7 @@ bool PPCInstrInfo::getFMAPatterns(
auto IsAllOpsVirtualReg = [](const MachineInstr &Instr) {
for (const auto &MO : Instr.explicit_operands())
- if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
+ if (!(MO.isReg() && MO.getReg().isVirtual()))
return false;
return true;
};
@@ -480,8 +480,7 @@ bool PPCInstrInfo::getFMAPatterns(
IsUsedOnceR = true;
}
- if (!Register::isVirtualRegister(MULRegL) ||
- !Register::isVirtualRegister(MULRegR))
+ if (!MULRegL.isVirtual() || !MULRegR.isVirtual())
return false;
MULInstrL = MRI->getVRegDef(MULRegL);
@@ -748,7 +747,7 @@ PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (Reg == 0 || !Register::isVirtualRegister(Reg))
+ if (Reg == 0 || !Reg.isVirtual())
continue;
// Find the toc address.
MachineInstr *DefMI = MRI->getVRegDef(Reg);
@@ -1541,7 +1540,7 @@ bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
// If the conditional branch uses a physical register, then it cannot be
// turned into a select.
- if (Register::isPhysicalRegister(Cond[1].getReg()))
+ if (Cond[1].getReg().isPhysical())
return false;
// Check register classes.
@@ -3378,10 +3377,10 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
if (!MI.getOperand(i).isReg())
continue;
Register Reg = MI.getOperand(i).getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
Register TrueReg = TRI->lookThruCopyLike(Reg, MRI);
- if (Register::isVirtualRegister(TrueReg)) {
+ if (TrueReg.isVirtual()) {
MachineInstr *DefMIForTrueReg = MRI->getVRegDef(TrueReg);
if (DefMIForTrueReg->getOpcode() == PPC::LI ||
DefMIForTrueReg->getOpcode() == PPC::LI8 ||
@@ -3852,7 +3851,7 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI,
MachineInstr **ToErase) const {
MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
Register FoldingReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(FoldingReg))
+ if (!FoldingReg.isVirtual())
return false;
MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg);
if (SrcMI->getOpcode() != PPC::RLWINM &&
@@ -5197,7 +5196,7 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
// If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
// need to fix up register class.
Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
- if (Register::isVirtualRegister(RegToModify)) {
+ if (RegToModify.isVirtual()) {
const TargetRegisterClass *NewRC =
MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
&PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 1b79774544c6..7d3a8b4ca252 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -164,7 +164,7 @@ static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
return nullptr;
Register Reg = Op->getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return nullptr;
return MRI->getVRegDef(Reg);
@@ -293,7 +293,7 @@ static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
for (unsigned PHIOp = 1, NumOps = VisitedPHI->getNumOperands();
PHIOp != NumOps; PHIOp += 2) {
Register RegOp = VisitedPHI->getOperand(PHIOp).getReg();
- if (!Register::isVirtualRegister(RegOp))
+ if (!RegOp.isVirtual())
return false;
MachineInstr *Instr = MRI->getVRegDef(RegOp);
// While collecting the PHI nodes, we check if they can be converted (i.e.
@@ -301,8 +301,7 @@ static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
unsigned Opcode = Instr->getOpcode();
if (Opcode == PPC::COPY) {
Register Reg = Instr->getOperand(1).getReg();
- if (!Register::isVirtualRegister(Reg) ||
- MRI->getRegClass(Reg) != &PPC::ACCRCRegClass)
+ if (!Reg.isVirtual() || MRI->getRegClass(Reg) != &PPC::ACCRCRegClass)
return false;
} else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI)
return false;
@@ -454,8 +453,7 @@ bool PPCMIPeephole::simplifyCode() {
case PPC::COPY: {
Register Src = MI.getOperand(1).getReg();
Register Dst = MI.getOperand(0).getReg();
- if (!Register::isVirtualRegister(Src) ||
- !Register::isVirtualRegister(Dst))
+ if (!Src.isVirtual() || !Dst.isVirtual())
break;
if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass ||
MRI->getRegClass(Dst) != &PPC::ACCRCRegClass)
@@ -533,7 +531,7 @@ bool PPCMIPeephole::simplifyCode() {
Register TrueReg2 =
TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
- if (!(TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)))
+ if (!(TrueReg1 == TrueReg2 && TrueReg1.isVirtual()))
break;
MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
@@ -552,7 +550,7 @@ bool PPCMIPeephole::simplifyCode() {
return false;
Register FeedReg1 =
TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
- if (Register::isVirtualRegister(FeedReg1)) {
+ if (FeedReg1.isVirtual()) {
MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1);
if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
return true;
@@ -585,8 +583,7 @@ bool PPCMIPeephole::simplifyCode() {
Register FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI);
Register FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI);
- if (!(FeedReg1 == FeedReg2 &&
- Register::isVirtualRegister(FeedReg1)))
+ if (!(FeedReg1 == FeedReg2 && FeedReg1.isVirtual()))
break;
}
@@ -654,7 +651,7 @@ bool PPCMIPeephole::simplifyCode() {
unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
Register TrueReg =
TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
- if (!Register::isVirtualRegister(TrueReg))
+ if (!TrueReg.isVirtual())
break;
MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
if (!DefMI)
@@ -664,7 +661,7 @@ bool PPCMIPeephole::simplifyCode() {
if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
return false;
Register ConvReg = DefMI->getOperand(1).getReg();
- if (!Register::isVirtualRegister(ConvReg))
+ if (!ConvReg.isVirtual())
return false;
MachineInstr *Splt = MRI->getVRegDef(ConvReg);
return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
@@ -718,7 +715,7 @@ bool PPCMIPeephole::simplifyCode() {
// If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
Register TrueReg =
TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
- if (!Register::isVirtualRegister(TrueReg))
+ if (!TrueReg.isVirtual())
break;
MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
@@ -729,8 +726,7 @@ bool PPCMIPeephole::simplifyCode() {
TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
Register DefsReg2 =
TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
- if (!Register::isVirtualRegister(DefsReg1) ||
- !Register::isVirtualRegister(DefsReg2))
+ if (!DefsReg1.isVirtual() || !DefsReg2.isVirtual())
break;
MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
@@ -780,7 +776,7 @@ bool PPCMIPeephole::simplifyCode() {
case PPC::EXTSH8_32_64: {
if (!EnableSExtElimination) break;
Register NarrowReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(NarrowReg))
+ if (!NarrowReg.isVirtual())
break;
MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
@@ -824,7 +820,7 @@ bool PPCMIPeephole::simplifyCode() {
case PPC::EXTSW_32_64: {
if (!EnableSExtElimination) break;
Register NarrowReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(NarrowReg))
+ if (!NarrowReg.isVirtual())
break;
MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
@@ -913,7 +909,7 @@ bool PPCMIPeephole::simplifyCode() {
break;
Register SrcReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
+ if (!SrcReg.isVirtual())
break;
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
@@ -929,7 +925,7 @@ bool PPCMIPeephole::simplifyCode() {
SrcMI = SubRegMI;
if (SubRegMI->getOpcode() == PPC::COPY) {
Register CopyReg = SubRegMI->getOperand(1).getReg();
- if (Register::isVirtualRegister(CopyReg))
+ if (CopyReg.isVirtual())
SrcMI = MRI->getVRegDef(CopyReg);
}
if (!SrcMI->getOperand(0).isReg())
@@ -1243,7 +1239,7 @@ static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
(*BII).getOperand(1).isReg()) {
// We optimize only if the condition code is used only by one BCC.
Register CndReg = (*BII).getOperand(1).getReg();
- if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg))
+ if (!CndReg.isVirtual() || !MRI->hasOneNonDBGUse(CndReg))
return false;
MachineInstr *CMPI = MRI->getVRegDef(CndReg);
@@ -1253,7 +1249,7 @@ static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
// We skip this BB if a physical register is used in comparison.
for (MachineOperand &MO : CMPI->operands())
- if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && !MO.getReg().isVirtual())
return false;
return true;
@@ -1627,7 +1623,7 @@ bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
return false;
Register SrcReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
+ if (!SrcReg.isVirtual())
return false;
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
@@ -1715,7 +1711,7 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
return false;
Register SrcReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
+ if (!SrcReg.isVirtual())
return false;
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
@@ -1731,7 +1727,7 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
assert(SrcMI->getOperand(1).isReg() &&
"EXTSW's second operand should be a register");
- if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+ if (!SrcMI->getOperand(1).getReg().isVirtual())
return false;
LLVM_DEBUG(dbgs() << "Combining pair: ");
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
index e3fe0ffd2a86..bf1c39a3a3a2 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
@@ -106,8 +106,8 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
if (!RA.isReg())
return true;
- return Register::isVirtualRegister(RA.getReg()) ||
- (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8);
+ return RA.getReg().isVirtual() ||
+ (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8);
}
// [addis rt,ra,si - ld rt,ds(ra)] etc.
case FusionFeature::FK_AddisLoad: {
@@ -116,7 +116,7 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
return true;
// Only check it for non-virtual register.
- if (!Register::isVirtualRegister(RT.getReg()))
+ if (!RT.getReg().isVirtual())
// addis(rt) = ld(ra) = ld(rt)
// ld(rt) cannot be zero
if (!matchingRegOps(SecondMI, 0, SecondMI, 2) ||
@@ -169,8 +169,7 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
// { ld,ldx } - cmpli 0,1,rx,{ 0,1 }
case FusionFeature::FK_LoadCmp2: {
const MachineOperand &BT = SecondMI.getOperand(0);
- if (!BT.isReg() ||
- (!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0))
+ if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0))
return false;
if (SecondMI.getOpcode() == PPC::CMPDI &&
matchingImmOps(SecondMI, 2, -1, 16))
@@ -181,8 +180,7 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
// { lha,lhax,lwa,lwax } - cmpi 0,L,rx,{ 0,1,-1 }
case FusionFeature::FK_LoadCmp3: {
const MachineOperand &BT = SecondMI.getOperand(0);
- if (!BT.isReg() ||
- (!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0))
+ if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0))
return false;
return matchingImmOps(SecondMI, 2, 0) || matchingImmOps(SecondMI, 2, 1) ||
matchingImmOps(SecondMI, 2, -1, 16);
diff --git a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
index 2ebbcc68f871..0504db239f67 100644
--- a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+++ b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
@@ -545,7 +545,7 @@ MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,
return Copy;
Register CopySrc = Copy->getOperand(1).getReg();
Subreg = Copy->getOperand(1).getSubReg();
- if (!Register::isVirtualRegister(CopySrc)) {
+ if (!CopySrc.isVirtual()) {
const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
// Set the Subreg
if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index eaa55af53507..7d913a77cc71 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -595,7 +595,7 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
case TargetOpcode::COPY: {
ResultOp = &Use.getOperand(0);
ResultReg = ResultOp->getReg();
- if (Register::isVirtualRegister(ResultReg) &&
+ if (ResultReg.isVirtual() &&
MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
VRM->hasPhys(ResultReg)) {
Register UACCPhys = VRM->getPhys(ResultReg);
diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
index 8a7d324ddfe1..837812ab85c4 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
@@ -128,7 +128,7 @@ namespace {
continue;
Register AddendSrcReg = AddendMI->getOperand(1).getReg();
- if (Register::isVirtualRegister(AddendSrcReg)) {
+ if (AddendSrcReg.isVirtual()) {
if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
MRI.getRegClass(AddendSrcReg))
continue;
@@ -209,7 +209,7 @@ namespace {
// legality checks above, the live range for the addend source register
// could be extended), but it seems likely that such a trivial copy can
// be coalesced away later, and thus is not worth the effort.
- if (Register::isVirtualRegister(AddendSrcReg) &&
+ if (AddendSrcReg.isVirtual() &&
!LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
continue;
diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index 04fc7667257e..365ba524a757 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -608,7 +608,7 @@ void PPCVSXSwapRemoval::formWebs() {
if (!isVecReg(Reg) && !isScalarVecReg(Reg))
continue;
- if (!Register::isVirtualRegister(Reg)) {
+ if (!Reg.isVirtual()) {
if (!(MI->isCopy() && isScalarVecReg(Reg)))
SwapVector[EntryIdx].MentionsPhysVR = 1;
continue;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index ff82a63214cd..cd1861c0f302 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -1210,7 +1210,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
Register Reg = MI.getOperand(I).getReg();
- Register PhysReg = Register::isVirtualRegister(Reg)
+ Register PhysReg = Reg.isVirtual()
? (VRM ? Register(VRM->getPhys(Reg)) : Register())
: Reg;
if (!PhysReg ||
@@ -1257,15 +1257,13 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
else {
Register DstReg = MI.getOperand(0).getReg();
Register DstPhys =
- (Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
- : DstReg);
+ (DstReg.isVirtual() ? Register(VRM->getPhys(DstReg)) : DstReg);
Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
: ((OpNum == 1 && MI.isCommutable())
? MI.getOperand(2).getReg()
: Register()));
if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
- Register::isVirtualRegister(SrcReg) &&
- DstPhys == VRM->getPhys(SrcReg))
+ SrcReg.isVirtual() && DstPhys == VRM->getPhys(SrcReg))
NeedsCommute = (OpNum == 1);
else
return nullptr;
@@ -1316,7 +1314,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
// Constrain the register classes if converted from a vector opcode. The
// allocated regs are in an FP reg-class per previous check above.
for (const MachineOperand &MO : MIB->operands())
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
+ if (MO.isReg() && MO.getReg().isVirtual()) {
Register Reg = MO.getReg();
if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass);
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index 28d01d53ccc5..7f3d8e8d311e 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -107,9 +107,8 @@ bool SystemZRegisterInfo::getRegAllocationHints(
auto tryAddHint = [&](const MachineOperand *MO) -> void {
Register Reg = MO->getReg();
- Register PhysReg = Register::isPhysicalRegister(Reg)
- ? Reg
- : Register(VRM->getPhys(Reg));
+ Register PhysReg =
+ Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
if (PhysReg) {
if (MO->getSubReg())
PhysReg = getSubReg(PhysReg, MO->getSubReg());
@@ -430,7 +429,7 @@ bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
MEE++;
for (; MII != MEE; ++MII) {
for (const MachineOperand &MO : MII->operands())
- if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.isReg() && MO.getReg().isPhysical()) {
for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
SI.isValid(); ++SI)
if (NewRC->contains(*SI)) {
diff --git a/llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp b/llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
index 277bbee83a6f..a1e0db692390 100644
--- a/llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
+++ b/llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
@@ -58,7 +58,7 @@ bool WebAssembly::isChild(const MachineInstr &MI,
if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
return false;
Register Reg = MO.getReg();
- return Register::isVirtualRegister(Reg) && MFI.isVRegStackified(Reg);
+ return Reg.isVirtual() && MFI.isVRegStackified(Reg);
}
bool WebAssembly::mayThrow(const MachineInstr &MI) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
index cf7d9ff2024b..60b1b3f5fc27 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
@@ -70,7 +70,7 @@ MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
std::string WebAssemblyAsmPrinter::regToString(const MachineOperand &MO) {
Register RegNo = MO.getReg();
- assert(Register::isVirtualRegister(RegNo) &&
+ assert(RegNo.isVirtual() &&
"Unlowered physical register encountered during assembly printing");
assert(!MFI->isVRegStackified(RegNo));
unsigned WAReg = MFI->getWAReg(RegNo);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
index 2814404b0222..70c187af73a5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
@@ -792,7 +792,7 @@ static void unstackifyVRegsUsedInSplitBB(MachineBasicBlock &MBB,
for (auto &MI : Split) {
for (auto &MO : MI.explicit_uses()) {
- if (!MO.isReg() || Register::isPhysicalRegister(MO.getReg()))
+ if (!MO.isReg() || MO.getReg().isPhysical())
continue;
if (MachineInstr *Def = MRI.getUniqueVRegDef(MO.getReg()))
if (Def->getParent() == &MBB)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 61cd0c2d7b33..4b24f7fdb118 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -375,7 +375,7 @@ static bool isSafeToMove(const MachineOperand *Def, const MachineOperand *Use,
!Insert->readsRegister(Reg))
continue;
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
// Ignore ARGUMENTS; it's just used to keep the ARGUMENT_* instructions
// from moving down, and we've already checked for that.
if (Reg == WebAssembly::ARGUMENTS)
@@ -471,8 +471,7 @@ static bool oneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse,
if (!MO.isReg())
return false;
Register DefReg = MO.getReg();
- if (!Register::isVirtualRegister(DefReg) ||
- !MFI.isVRegStackified(DefReg))
+ if (!DefReg.isVirtual() || !MFI.isVRegStackified(DefReg))
return false;
assert(MRI.hasOneNonDBGUse(DefReg));
const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg);
@@ -847,7 +846,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
assert(Use.isUse() && "explicit_uses() should only iterate over uses");
assert(!Use.isImplicit() &&
"explicit_uses() should only iterate over explicit operands");
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
// Identify the definition for this register at this point.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
index 7048f8926508..4ca262e248f7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
@@ -92,7 +92,7 @@ bool WebAssemblyRegisterInfo::eliminateFrameIndex(
MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
if (OtherMO.isReg()) {
Register OtherMOReg = OtherMO.getReg();
- if (Register::isVirtualRegister(OtherMOReg)) {
+ if (OtherMOReg.isVirtual()) {
MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
// TODO: For now we just opportunistically do this in the case where
// the CONST_I32/64 happens to have exactly one def and one use. We
diff --git a/llvm/lib/Target/X86/X86DomainReassignment.cpp b/llvm/lib/Target/X86/X86DomainReassignment.cpp
index 9d4338deca35..4e31bbc4345c 100644
--- a/llvm/lib/Target/X86/X86DomainReassignment.cpp
+++ b/llvm/lib/Target/X86/X86DomainReassignment.cpp
@@ -240,7 +240,7 @@ class InstrCOPYReplacer : public InstrReplacer {
// Physical registers will not be converted. Assume that converting the
// COPY to the destination domain will eventually result in a actual
// instruction.
- if (Register::isPhysicalRegister(MO.getReg()))
+ if (MO.getReg().isPhysical())
return 1;
RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()),
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index f54d2cf05a59..337b2b93b684 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -676,8 +676,7 @@ void X86ExpandPseudo::ExpandVastartSaveXmmRegs(
NewMI.add(VAStartPseudoInstr->getOperand(i + 1));
}
NewMI.addReg(VAStartPseudoInstr->getOperand(OpndIdx).getReg());
- assert(Register::isPhysicalRegister(
- VAStartPseudoInstr->getOperand(OpndIdx).getReg()));
+ assert(VAStartPseudoInstr->getOperand(OpndIdx).getReg().isPhysical());
}
// The original block will now fall through to the GuardedRegsBlk.
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index a83038f2b378..b7f0076f24ac 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5802,8 +5802,7 @@ unsigned
X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
const TargetRegisterInfo *TRI) const {
const MachineOperand &MO = MI.getOperand(OpNum);
- if (Register::isPhysicalRegister(MO.getReg()) &&
- hasUndefRegUpdate(MI.getOpcode(), OpNum))
+ if (MO.getReg().isPhysical() && hasUndefRegUpdate(MI.getOpcode(), OpNum))
return UndefRegClearance;
return 0;
@@ -9098,8 +9097,8 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
const MachineOperand &Op1 = MI.getOperand(1);
const MachineOperand &Op2 = MI.getOperand(3);
- assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
- Register::isPhysicalRegister(Op2.getReg())));
+ assert(Op2.isReg() &&
+ (Op2.getReg() == X86::NoRegister || Op2.getReg().isPhysical()));
// Omit situations like:
// %rsi = lea %rsi, 4, ...
diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
index 40ef69f3f3f3..e0018a0ea58b 100644
--- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
+++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp
@@ -200,8 +200,7 @@ static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N) {
static inline bool isIdenticalOp(const MachineOperand &MO1,
const MachineOperand &MO2) {
- return MO1.isIdenticalTo(MO2) &&
- (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
+ return MO1.isIdenticalTo(MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical());
}
#ifndef NDEBUG
diff --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
index 63240923792c..48b4b646dd3b 100644
--- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -36,7 +36,7 @@ static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
if (!MO.isReg() || !MO.isDef() || MO.isDead())
continue;
auto Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
if (MRI->getRegClassOrRegBank(Reg) == RC && MRI->getType(Reg) == Ty &&
@@ -92,7 +92,7 @@ static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
if (!MO.isReg() || !MO.isDef() || MO.isDead())
continue;
auto Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
auto UI = MRI->use_begin(Reg);
auto UE = MRI->use_end();
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